SAN JOSE, Calif. — Startup Keyssa claims that it is getting traction for its wireless chip-to-chip connection technology now in production. It also announced plans for its own version of virtualized I/O to run over the link.

The company that announced its 60-GHz technology last year expects to have a top-tier OEM show it running in a TV at CES. It is one of a half-dozen markets in which Keyssa design wins will ship in 2019.

A single Keyssa 65-nm chip fits in a 3-mm2 package and transmits up to 6 Gbits/second over about a centimeter, consuming about 70 to 100 mW. At least one maker of rugged storage servers aims to use up to 256 chips to create a 1.2-Tbits/s link.

At CES, a TV maker will show a 4-mm-thick 8K display that uses 32 Keyssa chips for a 96-Gbits/s connection to electronics housed in its stand. Before April, others will show a single wireless chip per display to create video walls.

Several users are attracted by the fact that the 60-GHz links penetrate plastics. Thus, an automotive company will use Keyssa in a plastic hinge to serve links to a rotating lidar. A robotic surgery company will use it to separate instruments and electronics by plastics to ease the job of sterilizing systems.

“These designs represent millions of devices — each 8K TV alone uses 68 devices in it,” said Steve Venuti, vice president of marketing.

The company, formed in 2009, has taken in $100 million in financing to date from investors including Dolby, Foxconn, Samsung, SK Hynix, and venture arms of Dolby and Intel. It is not currently planning another round.

Keyssa wireless communication diagram

A technique of muxing different protocols into slots with guaranteed bandwidth delivers the rough equivalent of virutal I/O. Click to enlarge. (Source: Keyssa)

New to its roadmap is a virtualized I/O capability that initially will be released before April as part of an FPGA evaluation kit. It allows multiple protocols to run over a single Keyssa link by dedicating parts of its 6-Gbits/s link to each protocol.

Keyssa claims that the technique creates a minor overhead measured in single digits and injects less than a few hundred nanoseconds of latency. The capability is not expected to add much to individual chip costs, which are currently below a dollar in high volumes.

— Rick Merritt, Silicon Valley Bureau Chief, EE Times