Andes and Gowin aim to capitalize
SANTA CLARA, Calif. — Momentum is growing in China for RISC-V, according to reports from two vendors at an event here. Andes detailed six cores it currently sells and four more in the works using the open-source instruction set architecture, and GoWin demonstrated FPGAs using them.
Overall, RISC-V shipments are still tiny compared to those of rivals such as Arm, but growth of its adoption and ecosystem “is moving in the right direction,” said one market watcher.
“In China, pretty much every company is asking for RISC-V, and they think it should include everything” Arm cores have, said Charlie Su, chief technology officer for Andes, a Taiwan-based core vendor that does 30% of its business in the People’s Republic.
So far, Andes has 12 licensees worldwide for its RISC-V cores. Their uses range from storage servers and fingerprint recognizers to several AI apps, he said.
“There’s a big push in China to adopt RISC-V for processors,” said Scott Casper, director of sales for Gowin, based in Guangzhou, China.
Several customers aim to use its FPGAs with an embedded Andes N25 core it will start making available this week. They are adopting it mainly as a management processor to help buffer data for computer vision and voice recognition apps, he said.
Much of the interest in the RISC-V architecture in China is said to be coming from a coalescing top-down consensus. The RISC-V Foundation recently hired an executive to promote the architecture in China.
For its part, Gowin evaluated three commercial RISC-V core providers before choosing Andes, “for the maturity of its tools and features and its understanding of the IP market,” Casper said. “If we tried something straight from Github we would still probably be without a solution,” he said, noting the complexity and lack of support for open-source code.
An executive from Taiwan’s Mediatek, an SoC vendor with significant business in China, spoke at the event but did not comment on the company’s plans for RISC-V. “In the end, RISC-V may not be cheap at all due to the effort to switch ISAs and other risk factors, but I believe with more choices there’s more healthy competition,” said Shichin Ouyang, director of technology at Mediatek USA.
The company uses processor IP from many vendors including legacy proprietary cores from Andes in Bluetooth and Wi-Fi basebands. Linley Gwennap of the Linley Group estimated Mediatek may have anywhere from five to 15 RISC-V projects currently in flight.
To date, Andes has released a family of six 32- and 64-bit N25 processors based on RISC-V, some supporting floating point units and running Linux. Low-end parts consume 4.1 microwatts/MHz while running at a GHz and fit into 0.033mm2 in a 28nm process.
The company is designing four new cores under code names Bumblebee and Aries. They will double performance and reduce area and power by as much as two-thirds, said Su. In addition, Andes proposed DSP extensions and is working on vector extensions and support for quad-core clusters for RISC-V, he said.
Andes chairs a RISC-V working group that will set a standard for DSP extensions. It also released an ASIC-like design tool to define and generate RTL code for new RISC-V instructions
Gwennap noted that one of the new 32-bit Andes N25 cores provides faster maximum data rate and lower area than Arm’s new Cortex-M33 while coming within 7% of its performance. “To win against Arm, you have to compete on performance, power and die area…and this shows RISC-V’s potential,” he said.
An Andes RISC-V core delivers similar performance to an Arm Cortex-M33 at much lower power and smaller die area. (Source: The Linley Group)
RISC-V has a negligible slice of the processor IP market ARM dominates today with 21.3 billion units shipped in 2017. However, it is gaining steam and is well suited to embedded, automotive and IoT apps that are tolerant of its lack of broad support from third-party software, he said.
RISC-V SoCs from startup Abee Semi are used in an estimated 20 million smartwatch and fitness bands from Huami, a company with ties to China handset maker Xiaomi. In the U.S., Nvidia plans to use RISC-V to replace proprietary management cores embedded in its GPUs. Western Digital said it will do the same in its storage products, driving sales of more than a billion units by 2020.
“If [RISC-V backer] Qualcomm uses it for embedded cores in its PMICs it could be in 800 million Snapdragons a year, so unit shipments could increase quickly,” said Gwennap.
Like Andes, core vendor Cortus is transitioning to RISC-V to take advantage of a broader ecosystem. Besides Andes and Gowin, the architecture has attracted at least three other vendors of commercial cores and FPGAs including Achronix, Microsemi and QuickLogic.
In software, the ecosystem would get a huge windfall if Google, a member of the RISC-V Foundation, decides to port Android to the architecture. In addition, it needs support from top RTOS vendors such as Green Hills, QNX and Wind River, said Gwennap.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times