50% lower power consumption than on 10nm, may beat TSMC to market
SAN JOSE, Calif. — The race is on to get the first chip made with extreme ultraviolet lithography out the foundry door.
Samsung said that it has taped out and is ramping multiple 7nm chips using EUV following a similar announcement earlier this month from its larger foundry rival, TSMC. Samsung also gave its supporting IP and EDA infrastructure a boost and detailed its packaging capabilities in an effort to catch up with TSMC’s ecosystem.
The South Korean giant also announced that it is sampling 256-GByte RDIMMs based on its 16-Gbit DRAM chips and plans for solid-state drives with embedded Xilinx FPGAs. But the 7nm news was the highlight of the event, a milestone fueled in part by its internal development of an EUV mask inspection system.
The 7LPP process will deliver up to a 40% shrink and up to 20% higher speeds or 50% lower power consumption compared to its 10nm node. Separately, Samsung said that it now has 50 foundry partners including Ansys, Arm, Cadence (which has digital and analog flows for 7 nm), Mentor, Synopsys, and VeriSilicon, which said that it taped out a chip in the 7nm process.
The process is said to have attracted customers who include web giants, networking companies, and mobile vendors such as Qualcomm. However, Samsung expects no customer announcements until early next year.
EUV systems supported 250-W light sources on a sustained basis since early this year at Samsung’s S3 fab in Hwaseong, South Korea, said Bob Stear, director of foundry marketing at Samsung. The power level drove throughput up to the needed 1,500 wafers/day for production. Since then, EUV systems have hit a peak 280 W, and Samsung targets 300 W, he said.
EUV eliminates a fifth of masks required with traditional argon-fluoride systems, raising yields. However, the node still requires some multi-patterning in base layers at the front-end-of-line, said Stear.
Samsung developed its own system to compare and fix expected and actual mask patterns to speed EUV into production. G. Dan Hutcheson of VLSI Research described it as a mask review system because it’s unclear if it is as automated as typical third-party inspection systems.
The 7-nm node will meet Grade 1 AEC-Q100 automotive standards by the end of the year. In packaging, Samsung is developing an RDL interposer that will enable up to eight HBM stacks on a single device. It is also working on a process to embed passives in a substrate to save space for data center chips.
Bob Stear shows a 7-nm EUV wafer from Samsung’s S3 fab. (Images: EE Times)
Both Samsung and TSMC will apply EUV probably only to two chip layers at 7nm, so far not using protective pellicles that are still in development, said Handel Jones, president of International Business Strategies. They will extend EUV to perhaps six layers at 5nm nodes, but that may not come until 2021, when pellicles will have sufficient durability and light-transmission capabilities.
“Samsung is about six months ahead with an EUV process because they have been using the systems with DRAM and logic, but TSMC is way ahead in enablement with IP and tools and is working with more customers such as AMD, Apple, HiSilicon, and Nvidia, among others,” said Jones.
Another analyst said that Cisco, a customer of the former IBM foundry business, is now working with TSMC for 7nm products. Qualcomm is expected to split its 7nm work between TSMC and Samsung.
Nevertheless, Jones forecasts that the South Korean giant’s revenues, on track to hit $90 billion this year, could leap to more than $150 billion by 2027. The prediction is based more on growth in its memory business, in which he estimates Samsung will rise to command 50% of DRAM and 45% of NAND sales.
Samsung is on track to start production of 5- and 4nm nodes before June, providing evolutionary improvements with the same device sets. PDKs for the nodes could be released before the end of the year, and a second shell for EUV production is being built next to the S3 fab, said Stear.
The three nodes will move the contact closer to and eventually over the gate to increase density and reduce metal pitches. It’s an approach that Intel previously discussed for its 10nm node that is still not in volume production.
“We’re doing contact-over-gate in steps,” said Stear. “It’s a hard problem to solve, as some are finding out.”
Samsung announced in May its plans to move to gate-all-around transistors, also described as nanosheets, for a 3nm node. It aims to drop nominal voltage to a new low to continue power savings. The first cut of a version 0.1 PDK for a 3nm node could be available by June.
Samsung has a laundry list of packaging options already available in house. Click to enlarge.
In its core memory business, Samsung said that it is sampling 256-GByte RDIMMs made with its 16-Gbit chips. The cards, running at DDR4 speeds up to 3,200 MHz and supporting 50-ns reads and writes, should be in production before the end of the year.
The chips are made in a 1y-nm process first described a year ago. It was not clear whether EUV is being applied to the 1y process. However, follow-on 1z and 1a nodes will increasingly use EUV, suggested Samsung’s head of DRAM development, Seong Jin Jang, in a talk here.
Samsung showed eight of the DIMMs running on an AMD Epyc server. They hit 3.2 million operations/second at 170 W compared to its existing 128-GB cards delivering 3.8 million ops/s at 225 W.
Ultimately, Samsung aims to boost DIMMs to 768 GBytes. It also aims to raise HBM data rates to 512 GB/s from 307 GB/s today. GDDR6 graphics memories will hit 22 Gbits/s from 18 Gbits/s today, and LPDDR memories will fall from 24 mW/GB to 12 mW/GB, he added, without providing time frames.
Separately, Samsung announced plans for smart solid-state drives (SSDs) using embedded Xilinx Zynq FPGAs to bolster performance 2.8x to 3.3x. The devices target a wide range of database, AI, video, and storage applications.
The SSDs will provide an easier way to scale performance than matching banks of standard FPGAs to separate accelerators, said the company. The products, still in a prototype phase, will use a range of densities and medium-grade FPGAs.
The smart SSD is, so far, only a prototype without specs or a delivery date
— Rick Merritt, Silicon Valley Bureau Chief, EE Times