Releasing EMIB (Embedded Multi-Die Interconnect Bridge) PHY specs in coming weeks
SAN FRANCISCO — Intel is weeks away from releasing a small but strategic piece of its proprietary packaging technology. It could become part of a future standard enabling a Lego-like design of SoCs out of chiplets.
The x86 giant is putting the final touches on a specification for its Advanced Interface Bus (AIB). AIB is a physical-layer block for the die-to-die connection in its dense, low-cost Embedded Multi-Die Interconnect Bridge (EMIB).
The company already licensed the spec to a handful of partners in a government research program. It aims to make AIB available royalty-free to anyone interested through a consortium.
If Intel can convince an existing consortium to offer AIB, it could be available within weeks. If the company needs to create a new consortium, the process could take as long as six months.
Low-cost, dense packages like EMIB are becoming increasingly important techniques for delivering high-performance chips at a time when traditional scaling is becoming more complex and costly. TSMC’s InFO, a rival approach, is used by the A-series processor in Apple’s iPhone.
Intel is keeping proprietary the secret sauce behind EMIB — the equipment and methods that it uses to build simplified bridges between chips. However, it aims to make AIB a standard interface for linking chiplets using any packaging technique, hoping to spawn an ecosystem of parts that it could tap for its own products.
Many others share the vision. “An Ethernet for chiplets is the most important goal for the CHIPS project” that Intel is part of, said Andreas Olofsson, program manager for the effort under the Defense Advanced Research Projects Agency (DARPA).
Another partner in the project, believed to be Micron, has developed two lightweight protocols that run over AIB — one for transactional and another for streaming data. The protocol and AIB are likely to be available from the same consortium eventually.
At least two other commercial efforts are in production with a separate but similar approach.
Marvell launched its MoChi initiative initially as a proprietary capability under founder and former chief executive, Sehat Sutardja. Startup zGlue announced last year a similar effort as a commercial offering targeting SoCs for the internet of things. In addition, Globalfoundries is said to be working with packaging houses on other alternatives.
EMIB sees use wth FPGAs, Xeon and Core
Whether the Intel approach or any other takes off remains to be seen. All tap into a growing desire to shave the increasing cost and complexity of SoC design.
Intel claims that EMIB can deliver a density of up to 500 I/Os per mm2, roughly comparable to TSMC’s 2.5D CoWoS approach but at a lower cost. CoWoS connects die through a large and relatively expensive silicon interposer beneath them while EMIB routes directly between chips without the large interposer.
TSMC’s InFO routes connections through a lower-cost organic package. It lacks the density of EMIB, which supports alignment pitches down to two microns today, but TSMC aims to drive InFO to that density level.
CoWoS offers the finest features today. GF, Samsung, and UMC offer similar 2.5D capabilities, said E. Jan Vardaman, a veteran packaging analyst and president of TechSearch International Inc.
Vardaman put TSMC’s InFO in a category with ASE’s FOCoS and Amcor’s SWIFT as less dense approaches using a redistribution layer on a carrier placed on a laminate substrate. Samsung is preparing a roughly similar approach, she added.
Intel first announced EMIB in 2014 as part of its foundry service that has yet to gain traction.
So far, the technology has been used only on Intel’s own chips. They include FPGAs linking to external SerDes and memories and to a Xeon processor.
The company also released a version of its Kaby Lake x86 processor linked to an AMD graphics chip and HBM memory that surprised and won praise from reviewers. Earlier this month, Intel said that it will explore using EMIB as part of the service that it acquired with eASIC.
For its part, the U.S. Department of Defense does not have trusted access to 2.5D packaging techniques, motivating its interest in the CHIPS program. One partner in the program is Micross, a U.S.-based packaging house capable of moderate-volume production and I/Os with five-micron pitches.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times