List of EUV related concerns shrinking rapidly as industry collectively pushes onward
ANTWERP, Belgium — A 20-year struggle to launch a next-generation lithography tool has entered its final phase as engineers race to unravel a rats nest of related issues. Despite complex problems and short deadlines to bring extreme ultraviolet (EUV) steppers into high volume manufacturing, experts remain upbeat.
The good news is many shoulders are pushing the wheel ahead. “In the past one company would take a lead with a new semiconductor technology, but now all the logic guys are jumping in, biting the bullet and taking the risks,” said An Steegen, executive vice president of technology and systems at Imec.
The research institute in Belgium is a long-standing collaborator with ASML, the developer of EUV in the Netherlands. Together with foundries and suppliers they now aim to work out the last major kinks in the room-sized systems that will print next-generation chips.
It’s like when the FinFET transistor emerged in 2008 as a significant but challenging vehicle for new performance gains, said Steegen in an interview at the Imec Tech Forum here.
“People compared the worst case of next node to the best case of the old node, but now all sides agree FinFETs are extremely high-performance devices. My lesson is to take it all with a grain of salt…there are enough features ahead to deliver improvements so SoC designers get what they want,” she said.
In a separate, informal conversation waiting in line for coffee at Imec’s headquarters, a 32-year veteran working on EUV put it simply. “There’s a lot of pressures right now…but we are making progress,” he said.
Indeed, Samsung’s foundry is racing to get EUV into production at 7nm before the end of the year. It aims to pull ahead of larger rival TSMC which is taping out many 7nm chips now using existing immersion steppers.
TSMC and GlobalFoundries are not far behind, aiming to ramp enhanced 7nm nodes with EUV early next year. Separately, Imec estimates DRAM makes will adopt EUV for their D14+ nodes, probably in 2021 when half pitches dip below 20nm.
Two of Imec’s focus areas now are helping smooth out line-edge roughness and eliminating so-called stochastics, random errors that create missing or kissing contacts. The errors were first reported earlier this year at 15nm dimensions key for a next-generation 5nm node, but researchers now say they also see them at 7nm.
Steegen expects hybrid solutions will emerge. They will use a combination of scanner settings, resist materials and post-processing techniques that stitch broken lines, smooth jagged ones or fill out missing contacts.
Foundries can apply higher doses of EUV light, say 80 millijoules/cm2, to widen a process window, but that will slow throughput. “Deciding the peak dose for the first implementations is up to the foundries,” Steegen said.
Hybrid solutions and relaxed design rules
For its part, Imec is working to predict and map where stochastics are likely to emerge in a design, providing a view to a process window. Finding the defects typically involves heavy use of fast e-beam inspection systems.
As features approach single nanometer dimensions, researchers are beginning to attribute errors to minute details. For example, the number of photons in an EUV exposure impacts chemically-amplified resists, and performance of other resists can vary with the orientation of their embedded metallic molecules
“Not every resist behaves the same, and how they behave with different underlays is also unique…we are still going through some fundamental learning,” she said.
To ease its migration, Globalfoundries is phasing in EUV on just five layers of metal at relatively relaxed 7nm pitches. “We can operate at lower doses for good throughput,” said Gary Patton, chief technologist of the company, in an interview here.
Later this year, GF will use immersion steppers to tape out its first 7nm chip, an AMD processor. An IBM processor will follow with ASICs coming in 2019, Patton said.
GF made the size of its 7nm pitches and SRAM cells similar to those of TSMC to let designers like AMD use both foundries. AMD “will have more demand than we have capacity, so I have no issues with that,” he said of AMD using the Taiwan foundry.
However, GF will skip the 5nm node, as it did the 10nm node, believing it will have modest incremental gains. It is seeking financial and technology partners for its follow on, likely a 3nm node.
Staying optimistic amid many challenges
Despite the challenges Patton remains upbeat. The smartphone slowdown has morphed into an AI era with “an explosion of new fabless companies.” Meanwhile, GF’s fully depleted silicon-on-insulator (FD-SOI) process will have 75 design partners by the end of the year serving 36 current design wins, he said.
“A number of people were sitting on the sidelines last year to see if FD-SOI was real, and now it clearly is,” he said, supporting designs down to 0.4V and ramping an automotive grade-2 version this fall.
GF and Imec execs remain bullish on the semiconductor road map overall. However, some designers are starting to speak out publicly that speed gains have generally ended and area and power advantages are lessening from node to node.
For its part, Imec is helping foundries develop a laundry list of performance boosters to compensate. They include simplified cell tracks, buried power rails and on-die circuit stacks.
“In general, I’m not seeing diminishing returns. I’m optimistic for the 3m and 2nm logic nodes and the memory road map. We have enough things in the basket…so designers will see area scale, but they might have to make some changes to their designs,” Steegen said.
As a result, Imec’s core program for chip scaling continues to grow at a 5-10 percent annual rate. “Ten years ago, we were expecting our work in advanced CMOS would level off because of consolidation in industry, but the contrary has been true,” said Imec’s chief executive, Luc Van den Hove, noting the program is expanding with new projects in AI accelerators and DNA storage.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times