SAN JOSE, Calif. — Researchers reported random defects appearing in extreme ultraviolet (EUV) lithography at 5nm nodes. They are applying an array of techniques to eliminate them, but so far see no clear solution.

The news comes as Globalfoundries, Samsung and TSMC are racing to rev EUV systems up to high availability with 250W light sources for 7nm production next year. The defects show there’s no panacea for the increasing costs and complexity of making semiconductors.

The latest EUV scanners can print the 20nm and larger critical dimensions that foundries plan at 7nm, said Greg McIntyre, a patterning expert from the Imec research institute in Belgium. However, their ability to make finer lines and holes is unclear, he said in a talk at an annual conference for lithographers here.

Optimists such as McIntyre believe a basket of solutions will emerge for the so-called stochastic effects. Some skeptics see the results as one more reason to doubt the expensive and long-delayed EUV systems will become mainstream tools for chip makers.

A retired Intel lithographer predicted engineers will be able to create 5nm and even 3nm devices by using two and three passes with an EUV stepper. But a rising tide of chip defects ultimately will drive engineers to new, fault-tolerant processor architectures such as neural networks, said Yan Borovodsky in a keynote at the event.

The latest defects are cropping up at critical dimensions around 15nm needed to make 5nm chips for foundry processes targeting 2020. EUV maker ASML is preparing a next-generation EUV system for printing finer features, but those systems won’t be available until about 2024, it said at the event last year.

5nm EUV defects
Imec researchers reported on random defects with EUV at 5nm
Source: Imec

The random defects take many forms. Some are imperfectly made holes; others are tears in lines or shorts where two lines or two holes meet. Given their tiny dimensions, researchers sometimes spend days just to find them.

McIntyre outlined the challenges finding and eliminating the errors. For example, some researchers are proposing this week a standard way to measure the roughness of lines, one key to understanding the defects.

Another issue is its unclear exactly what happens to resist materials when hit with EUV light. “It’s still unknown how many electrons are generated and what kinds of chemistries are created…we’re a little way from a full understanding of the physics, so we’re doing more experiments,” McIntyre said, noting researchers have tested as many as 350 combinations of resists and process steps.


Yield a top concern at 7nm, 5nm nodes

“Manufacturing guys will get beat up incredibly over yield loss…if I was going to be responsible for this, I’d say it’s time to retire,” quipped one veteran lithographer during a Q&A session about the 5nm defects.

A Globalfoundries technologist provided a more upbeat but sober assessment in another keynote. “It’s been a lot of hard work, and there’s a lot more hard work to come,” said George Gomba, a vice president of research at GF, recalling a nearly 30-year history of work on EUV.

Today’s NXE 3400 systems are “not meeting some road map conditions we desire, so there is still some uncertainty [at 7nm]. If we do not make productivity and availability improvements, we may only be able to use EUV for the most aggressive processors,” Gomba said.

He noted the random defects at 5nm include subtle 3D breaks and tears such as notches in lines. Gomba also called for more work on so-called actinic systems that inspect EUV masks before lithographers cover them with protective pellicles.

“To get full use of EUV we will need actinic inspection systems [still in development], maybe complementing e-beam mask inspection systems” that are available today, he said.

GlobalFoundries EUV Roadmap
Globalfoundries shared its views of where and when to insert EUV. (Dark green boxes indicate high numerical aperature EUV is favored.)
Source: GlobalFoundries

In an interview, Borodovsky said another factor that may be contributing to the 5nm defects is a lack of homogeneity in the current EUV resist materials. Separately, he said he supports work on direct e-beam writers because the complex phase-shift masks EUV uses ultimately will balloon to 8x the price of today’s immersion masks.

Multibeam, a company formed by Lam Research founder David Lam, recently snagged $35 million in government funding for his e-beam technology. He hopes to have commercial systems in 2.5 years for niche applications, but versions suitable for high volume manufacturing will take much longer, Lam said.

By 2024, defects could become so widespread that conventional processors will not be able to be made in leading-edge processes, Borodovsky said. Experimental chips using memory arrays with embedded computing elements could be more fault-tolerant, citing IBM’s True North chip and work by HP Labs with memristors.


Imec shows a roadmap to 2030
IMEC Roadmap
Next-gen EUV could be in use by 2025, Imec said.
Source: Imec


Globalfoundries provides a look back at EUV
IMEC Roadmap
One keynoter gave a brief overview of major milestones in the nearly 30 years of R&D on EUV
Source: GlobalFoundries

IMEC Roadmap

— Rick Merritt, Silicon Valley Bureau Chief, EE Times