New Trench Power MOSFET Tuned for Higher Ruggedness

Article By : Filippo Scrimizzi and Giusy Gambino, STMicroelectronics

Power MOSFET devices are widely used in electronic systems driven in linear mode as voltage-controlled resistors, thanks to the benefits they offer in terms of EMI and overall system cost.

Power MOSFET devices are widely used in electronic systems driven in linear mode as voltage-controlled resistors thanks to the benefits they offer in terms of electromagnetic interference (EMI) and overall system cost.

In linear mode operation, the MOSFETs are forced to withstand harsh working conditions with high drain current (ID) and high drain source voltage (VDS) and then manage huge power levels. Then these devices have to meet not only some technological requirements to increase the ruggedness but also thermal management constraints to avoid the thermal runaway.

STMicroelectronics (ST) has introduced a new 100V power MOSFET manufactured with an advanced STPOWER STripFET F7 technology and housed in H2PAK package. The device is tuned for rugged forward bias safe operating area (FBSOA) operation, where high power levels are required with high voltage drops.

The wide SOA capability is the result of the STripFET F7 technology optimization in terms of both tuning of the gate-source voltage (VGS) to avoid current focalization and setting of the threshold voltage (VGS(th)) and transconductance (Gfs) to reduce the thermal dissipation. Then the MOSFET is thermally stable for a wider range of operating conditions into the SOA. The new STH200N10WF7-2 power MOSFET is tailored for safety switch for battery insulation and power distribution, in-rush current limiters, e-fuse, linear driven motor controller, load switch and hot swap applications.

Rugged Behavior in Linear Mode

The new wide SOA MOSFET (STH200N10WF7-2) offers superior performance compared to an equivalent trench device for higher current capability under the same operating conditions, as shown in Figs. 1 and 2.

Figure 1: SOA diagram for a standard trench MOSFET.

Figure 2: SOA diagram for the wide SOA trench MOSFET.

Whilst the standard trench MOSFET at 20V is able to withstand a current of 2.5A with a 10ms pulse time, the new wide SOA STH200N10WF7-2 can handle a current of 6.5A at the same conditions.

The improved performance is the result of a technology optimization aimed at ensuring almost flat current curves at high VDS and also a self-balanced current limitation over time, as shown in Figs. 3 and 4 [1].

Figure 3: Measured output characteristics of the wide SOA MOSFET.

Figure 4: Simulated drain current stability over time.

Compared to the standard trench MOSFET and the best competitor device available on the market, the wide SOA MOSFET exhibits excellent thermal stability for a wider range of operating conditions in linear mode.

As a result of the design and optimization trade-off, the STH200N10WF7-2 features a low current gain at lower gate-source voltage (VGS) to limit the current increase and then the thermal runaway in linear mode operation while increasing it at higher VGS values to reduce the on-resistance (RDS(on)) in switching conditions, as shown in Figure 5.

Figure 5: Simulated transfer characteristics.

Thanks to this feature, after limiting the surge inrush current pulse in linear mode at start up, the wide SOA device can also be driven in PWM (Pulse Width Modulation) mode.

Linear Mode Performance

The key parameter to define the linear mode performance of a power MOSFET is the drain current thermal coefficient (TC), defined in the following equation:

where ID is the drain current and T the temperature of the device.

This coefficient represents the ability of the device to self-balance the current control at both high temperatures and voltages. It is a technology-dependent parameter, linked to the transfer characteristics of the MOSFET and their trend over temperature (Figure 6).

Figure 6: Transfer characteristics of a power MOSFET (at different temperatures).

The three transfer curves intersect at a crossing point, called zero temperature coefficient or zero tempco (ZTC):

▪ for VGS = VGS(ZTC), the device current remains stable with temperature;

▪ for VGS > VGS(ZTC), as the device temperature increases, the drain current tends to decrease, reaching conditions of thermal stability;

▪ vice versa, for VGS < VGS(ZTC), as the device temperature increases, the drain current continues to increase thanks to the lower threshold voltage which has a negative coefficient versus temperature; consequently, when a small area of the die becomes hotter than the adjacent zone, it conducts more drain current, thus creating more heat and pushing the device to failure (thermal runaway), if the appropriate limitations are not set [1].

A comparison between the thermal coefficient of the standard STripFET F7 MOSFET and the new wide SOA STH200N10WF7-2 is below reported (Figure 7).

Figure 7. Thermal coefficient of the standard device and the new MOSFET at different VDS.

When TC is either zero or negative, as the temperature increases, the drain current decreases and the device works in conditions of thermal stability. However, even if TC is positive, the device can work without failing: this depends on the thermal capacity of the entire die to catch away the heat per unit area. If the heat produced over time can be completely extracted from the device, then the power MOSFET works in safe conditions [2].

The “low ID and high VDS” region is the most unsafely zone of the device SOA in linear mode: in fact, the low ID region is typically the one in which the power MOSFETs have the highest positive thermal coefficient and, at the same time increasing VDS, the generation of power and heat grows significantly [2].

Then, fixed the thermal coefficient curve, the device will become potentially more unstable at high VDS level. The thermal instability condition can be written also as:

where TC is the thermal coefficient and Rth is the thermal resistance.

The temperature distribution on the die at different VDS levels is shown in Figure 8.

Figure 8: Die temperatures @ VDS = 10V (left), VDS = 15V (center) and VDS = 20V (right).

By increasing the VDS voltage from 10V to 20V, the temperature distribution at die level becomes much less uniform with a clear focusing in a very small die area. This area heats up more than contiguous parts: here the localized gate-source threshold voltage (VGS(th)) reduction together with the increase of the drain current (which in turn generates more heat reducing further the VGS(th)) could cause the thermal runaway and the failure of the device.

When VDS increases, due to the current focusing in a small area and therefore the reduction of the active area of the device, the thermal resistance grows up, thus reducing the power level that the device can handle safely (Figure 9).

Figure 9: Thermal resistance increase at higher VDS.

The thermal resistance (Rth) of the semiconductor package is the measure of the material ability to transfer the heat far from the junction (or die) to the ambient environment or PCB.

The lower the thermal resistance is, the faster and better the heat dissipation from the die is. For the low voltage power MOSFETs, the thermal resistance is dependent on several factors: device characteristics, such as package type, die size, die thickness. Some imperfections of the die-attach process (voids) can also dramatically change the device thermal resistance with consequent temperature increase in small areas of the die. Then the non-uniformity in the die process may generate localized hot spots that could eventually cause the device fail. An additional risk factor is the temperature rise. In fact, silicon thermal resistance increases with temperature, worsening the heat dissipation in the area far from the junction. Non-uniformity in the die-attach process together with high temperatures can generate high Rth values in very small die areas, thus creating the condition for thermal runaway and device failure [3].

Experimental Verification

The ruggedness of the STH200N10WF7-2 MOSFET has been experimentally verified by adopting the testing circuit shown in Figure 10.

Figure 10: Testing circuit.

The following test conditions have been considered:

Vcc = VDS = 40 V

VDZ = 36 V

R = 1kΩ.

The first test has been performed by applying a pulse with a duration of 10 ms and increasing the ID current until the device fails. The measured waveforms relevant to the standard MOSFET and the wide SOA device just before failure are shown in Figs. 11 and 12.

Figure 11: Measured waveforms for the standard device at a fixed pulse duration.

Figure 12: Measured waveforms for the wide SOA device at a fixed pulse duration.

Experimental data confirm the excellent current capability of the wide SOA MOSFET which is capable of withstanding a current of 29.5A compared to the current of 1.2A managed by the standard device.

A second test has been carried out by applying a current in the range of 20A and increasing the pulse duration until the device fails. The measured waveforms for both devices just before failure are shown in Figs. 13 and 14.

Figure 13: Measured waveforms for the standard device at a fixed drain current.

Figure 14: Measured waveforms for the wide SOA device at a fixed drain current.

The test results demonstrate the high ruggedness of the wide SOA MOSFET which is able to survive for 20ms under the stressful linear mode conditions whereas the standard device can work for 800μs only before failing.

The results of such empirical trials have been projected on the SOA curves both in terms of power capability and pulse duration, as reported in the following figures (Figs. 15 and 16).

Figure 15: SOA projection of the empirical trial in terms of power capability.

Figure 16: SOA projection of the empirical trial in terms of pulse duration.

Both the power level and pulse duration demonstrate the higher ruggedness of the wide SOA technology. One of the best competitor’s device has failed at much lower power level and shorter time pulse duration, as shown in Figure 17.

Figure 17: Measured waveforms for the best competitor device.

Experimental results show that the competitor device can withstand a current of 10.4A at 30V for 10ms only.


The new wide SOA MOSFET technology exhibits an excellent performance in linear mode working conditions thanks to the high ruggedness and thermal stability which prevents the thermal runaway. In addition, the new device driven in fully saturation region (linear resistive behavior) is also suitable for switching applications, where the linear mode occurs during the transition phases only. The STH200N10WF7-2 is the best choice to design safer electronics systems.


  1. A. Consoli, F. Gennaro, A. Testa, G. Consentino, F. Frisina, R. Letor and A. Magrì, “Thermal instability of low voltage power MOSFET’s”, IEEE Transaction on Power Electronics, vol. 15, no. 3, May 2000.
  2. G. Consentino and G. Bazzano, “Investigations on Electro-Instability of Low Voltage Power MOSFETs: Theoretical Models and Experimental comparison results for different structures”, PET 2004 Conference, Chigaco 2004.
  3. A Raciti, F. Chimento, S. Musumeci, G. Privitera, “A New Thermal Model for Power MOSFET Devices Accounting for the Behavior in Unclamped Inductive Switching”, Special Issue on Reliability Issues in Power Electronics (Si and Wide Band Gap Devices, Interconnections, Passives, Analysis and Applications) on Microelectronics Reliability, ELSEVIER Editor 58 (2016) Conf. Rec. 2019 21st European Conference on Power Electronics and Applications (EPE ’19 ECCE Europe), 3-5 Sept. 2019, Genova, Italy.


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