IBM Research and CEA-Leti show their work on nanosheet architectures to drive the silicon performance needs of HPC applications...
A popular topic at technical conferences is around new architectures to address new high-performance compute needs. Pushing transistors to even smaller and smaller technologies to follow Moore’s Law just won’t be possible at some point, the argument goes, both in terms of process technology limitations and more importantly, cost.
At this year’s 2020 Symposia on VLSI Technology and Circuits, under the theme of “The Next 40 Years of VLSI for Ubiquitous Intelligence”, a number of talks focused on developing advanced circuit design and application platforms to enable such ubiquitous intelligence. IBM Research and CEA-Leti showed their work on nanosheet architectures to drive the silicon performance needs of such applications.
A team from IBM Research presented its work on a new nanosheet architecture that successfully creates pockets of air, called air spacers, around a transistor gate, which work universally on any device architecture and provide a more practical, compatible way to enable devices to consume less power and perform better. In fact, they have shown that applying this air spacer on a 7 nm node device delivers better performance gains and power reduction than scaling the device to 5 nm node.
Meanwhile, researchers at CEA-Leti said they had fabricated a new stacked seven-layer gate-all-around (GAA) nanosheet transistor architecture as an alternative to FinFET technology. With widths ranging from 15nm to 85nm, the team summarized its results in a paper at the conference.
Air spacers with better performance on 7nm compared to 5nm
IBM Research presented its work on a universal air spacer compatible with different transistor architectures, whether it’s a fin field-effect transistor (FinFET) or a nanosheet device architecture. In a paper, “Improved Air Spacer Co-Integrated with Self-Aligned Contact (SAC) and Contact Over Active Gate (COAG) for Highly Scaled CMOS Technology,” its researchers described how the new air spacer reduces effective capacitance – a critical factor impacting the characteristics of CMOS devices — by 15% through a reduction in the air spacer’s dielectric constant, leading to performance gains and power reductions at the same time. Although SAC and COAG have been adopted in FinFET technology to reduce the footprint of transistors and standard cells, co-integrating air spacers with SAC and COAG has been challenging.
The spacer is an isolation layer between a gate and the contacts for source and drain in the transistor — essentially, an electronic switch. When the gate is on, electricity flows from the source to the drain, and the gate serves as a valve. The spacer ensures the gate controls only the flow and that the gate and the source and drain are electrically isolated. Without the spacer, the gate cannot serve as a valve.
IBM’s researchers positioned their improved air spacer as a viable approach to enhance energy efficiency and performance of advanced CMOS technology by reducing parasitic capacitance, the unwanted capacitance between the parts of an electronic component or circuit due to their proximity to one another. The paper introduces a new process to form air spacers and provides a practical approach to enabling an electronic device to consume less power while achieving better performance.
In fact, introducing the new air spacer module into 7nm FinFET produces more performance gains than more costly and disruptive scaling of FinFET to 5nm. The researchers expect their work will help pave the way for their technology’s adoption in FinFET and nanoSheet transistors in the coming years.
Kangguo Cheng, one of the research team at IBM who presented the project, told EE Times, “The previously announced air spacer in 2016 was formed during the early stage of the device fabrication, before middle-of-line (MOL) contact formation. We call it the air spacer early (AS-Early) scheme. AS-Early can be simply plugged into a CMOS flow, but has challenges when it is scaled down to 7nm node and beyond. As an example, it is not compatible with contact-gate-over-active, an essential technology element for reducing the standard cell size of CMOS at 7nm node and beyond.”
He added, “In our recently-announced air spacer scheme, the air spacer is formed during the late stage of the device fabrication, after middle-of-line (MOL) contact formation. We call it the air spacer late (AS-Late) scheme. The new scheme overcomes the scaling issue of AS-Early. It is fully compatible with self-aligned contact and contact-gate-over-active.”
Cheng also said that another distinct difference between the two schemes is that the AS-Early scheme can reduce the parasitic capacitance of planar or FinFET devices, but it is less effective for the emerging gate-all-around (GAA) devices such as nanosheet and nanowire devices. In contrast, the new scheme presented at the conference works effectively for all device architectures.
New GAA nanosheet architecture with 7 level stacked silicon
Meanwhile, CEA-Leti demonstrated fabrication of a new gate-all-around nanosheet device as an alternative to FinFET technology targeting high-performance (HPC) applications such as smartphones, laptops, and mobile systems with data collection and processing involving low-power and high-speed operation.
Its researchers fabricated GAA nanosheet transistors with seven levels of stacked silicon channels — which it claims is more than twice as many as state-of-the-art today — with widths ranging from 15nm to 85nm. The results were summarized in the paper, “7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing”.
One of the authors of the paper, CEA-Leti scientist Sylvain Barraud, said the seven levels of stacked nanosheet GAA transistors fabricated using a replacement metal gate process, inner spacer and self-aligned contacts show excellent gate controllability with extremely high current drivability (3mA/μm at VDD=1V), and a 3x improvement in drain current over the usual two levels stacked nanosheet GAA transistors.
He explained, “By increasing the number of stacked-channels, we increase the effective width of the device for a given layout footprint. Increasing the effective width induces higher drive current. This is why the DC performance of our devices is better than leading-edge devices.” Barraud said CEA-Leti’s demonstration was based on a “replacement metal-gate” process developed for FinFET.
“We added specific modules for GAA structures on this FinFET route and we showed that for the same surface occupation we can propose an alternative to FinFET technology due to a gate-all-around configuration.” He added that GAA structures offer many advantages over FinFET, such as better gate control and higher DC performance, thanks to higher effective channel width. “In addition, the wide range of variable nanosheet widths allows more design flexibility, which is not possible for FinFET because of its discrete number of fins.”