Nepes has successfully produced the world's first 600mm x 600mm large panel level packaging (PLP) using Deca's M-Series fan-out technologies.
Nepes Laweh Corp. has successfully produced the world’s first 600mm x 600mm large panel level packaging (PLP) using Deca’s M-Series fan-out technologies.
Nepes Laweh had a grand opening of the Cheongan Campus PLP Line on December 7 with the presence of the Minister of Trade, Industry and Energy, the Governor of Chungcheongbuk-do, and client representatives and partners. The company announced that the fan-out-panel level packaging (FOPLP) line completed customer certification in the third quarter, and secured a stable yield and entered full-scale mass production.
The recently opened Cheongan Campus is built on a 186,000m2 of land. The campus is a PLP fab facility that can produce up to 96,000 600mm panels with PLP per year. Nepes is expected to provide high-density packaging solutions required for advanced system semiconductors for each application, such as smartphones, automobiles, and IoT, based on the customer needs.
“FOPLP is the best packaging solution for high-end semiconductors, which has resulted from long cooperation with global partners in various industries such as materials, parts, and equipment,” said Chilhee Chung, Chairman and Director of semiconductor division of Nepes.
“We’re pleased to be working with Nepes to bring the industry’s largest format 600mm square panel to volume production,” commented Tim Olson, CEO of Deca. “With initial production focused on single and multi-die packages for leading Smartphone producers, the future is heterogeneous integration of chiplets using Deca’s Gen 2 technology. A recent customer application with 10 embedded chiplets was designed into a 36mm x 36mm package. Such a large device is limited to 73% maximum utilization on 300mm round format due to edge losses. On 600mm, the utilization jumps to 92%, delivering greater than 25% cost reduction on area utilization alone.”
One of the next-generation packaging technologies, fan-out technology can increase the number of input/output terminals by placing semiconductor I/Os outside the die. Nepes’ 600mm square panel makes it possible to minimize the discarded edges and can produce five times as many chips as one 300mm round panel.