NeoLogic's chip design technology is fully compatible with the existing manufacturing as well as EDA tools so it can seamlessly fit into any PnR design flow as well as chip fabrication.
Moore’s Law extrapolated that the economy of scale of CMOS VLSI manufacturing due to transistor gate length scaling down by a factor of 0.7X every technology generation would drive down the cost of microprocessors by a factor of 2x on each technology node. This extrapolation no longer applies to the chip manufacturing market since the introduction of FinFET technology.
Just recently, in response to PC World’s editor Gordon Ung’s question during a virtual press session, Nvidia CEO Jensen Huang, said that “Moore’s law is dead” ,”and the ability for Moore’s Law to deliver twice the performance at the same cost, or at the same performance and half the cost, every year and a half is over. It’s completely over.”
“The idea that a chip is going to go down in cost over time, unfortunately, is a story of the past,” Jensen added. Moreover, he pointed out that “a 12-inch wafer is a lot more expensive today than it was”, “and it’s not a little bit more expensive; it is a ton more expensive.”
While the progress of the economy of scale of chip manufacturing is losing steam, data center workloads of AI\ML computing, HPC, data analytics, and the like significantly outpace the advancement of computing power. Footprint and power constraints of server processors, GPUs, AI accelerators, automotive, IoT, and other applications press chip designers to deliver maximum computation efficiency (i.e. computation power per Watt) but they struggle hard to keep the pace.
Avi Messica (left) and Ziv Leshem (right), Co-founders of NeoLogic.
“CMOS is considered by many as the last frontier of logic,” says NeoLogic CEO Dr. Avi Messica. He says that since the industry has switched from single-transistor logic (e.g. Intel 80286 nMOS microprocessor) to nMOS-pMOS pair logic (e.g. Intel 80386, CMOS microprocessor) in the early eighties of the past century, no new paradigm has commercially emerged.
NeoLogic has invented Quasi-CMOS; an integrated approach to chip design that uses single-transistor logic with standard CMOS logic to deliver significant area and power saving at any technology node. Messica says that many startups, as well as large players, have presented interesting new directions for the post Moore’s Law era such as new logic devices (e.g. Coulomb Blockade Logic, Spintronic-based Logic etc.) or new materials-based transistors (e.g. Graphene, MoS2 and the like) but it seems that Si-based field effect transistors (FET) will dominate and keep us going in the future in the form of Gate-All-Around (GAA) aka as ribbon\nanosheet FET and other 3D approaches.
NeoLogic CTO Ziv Leshem adds that none of the non-Si innovative approaches even come close to the multi-trillion-dollar CMOS manufacturing infrastructure. “So unless we are talking about some niche market (e.g. AlGaAs HEMTs for micro\mm waves communications or radar),” Leshem says. “It seems that Si-based FET technology is the only generic microprocessor technology that humanity has.”
NeoLogic is a Netanya-based (Israel) advanced logic company founded in early 2021 by two semiconductors industry veterans who bring both chip design and fabrication expertise to the company. The company plans to design and sell processors with unmatched power-performance-area (PPA) using its technology. However, until then, it seeks to monetize some of its already-developed blocks – under the brand name NeoMOS – via IP-licensing agreements. It currently offers various NeoMOS blocks of 16nm and 5nm technology nodes that the company claims to be the world’s most efficient in terms of power and area.
“Chips design is a lengthy, laborious, expensive, and complex process” says Leshem. “Our chip design technology is fully compatible with the existing manufacturing as well as EDA tools so it can seamlessly fit into any PnR design flow as well as chip fabrication.”
He adds that NeoLogic is sampling Hard-IP blocks with a selected group of tier-1 customers. Moreover, chip designers can mix and match Quasi-CMOS with standard CMOS designs. Customers from different fields and applications including DSP, AI acceleration, crypto-mining, industrial, communication, and automotive as well as other sectors find NeoMOS very attractive because it allows them to design chips with PPA that is superior to standard CMOS. Moreover, NeoMOS can save its customers the need to switch to a more advanced technology node. By sticking to their current technology node but designing with NeoMOS, NeoLogic customers can get the benefits of at least one generation ahead without migrating to it.
Topology as key for advanced logic
In the past 40 years, the semiconductors industry applied a technological\fabrication approach of scaling down the area of transistors in each generation by the introduction of advanced Litho-Etch technology thereby increasing the transistor packing density every new generation.
According to Messica, the 2nm, 3nm, 5nm nomenclature is merely marketing terms and does not represent the gate length as it used to be in the past. “Improvement in sub-10nm generations is achieved by pushing the limits of the standard cell by reducing its height, gate contact pitch and the like and not by scaling down the transistors. One of the trade-offs of this is the low wafer yield of these nodes which results in the high wafer cost that Jensen Huang pointed at,” he says.
NeoLogic adopted a different approach: complexity reduction. Instead of reducing the area of transistors, it reduces the number of transistors per circuit. Thereby increasing packing density by a reduction of the transistors count per logic function. This is accomplished via using circuit topologies and gates different than traditional CMOS.
To exemplify, on the left pane is the optimal CMOS topology for the addition of two binary numbers with a complexity of 28 transistors. The right pane depicts NeoLogic’s implementation for the same circuit comprising of only 18 transistors. Leshem says that trying to use NeoLogic’s topology in CMOS will result in far more than 18 transistors. It is the combination of NeoMOS and a specific circuit topology that results in a more efficient implementation of logic functions.
Left: CMOS 28 transistors implementation of a one-bit full adder
Right: NeoLogic’s 18 transistor implementation of a one-bit full adder
“We are getting into a renaissance period in semiconductors,” Messica says. “New innovative approaches for advanced logic, beyond Moore’s Law era, are emerging and it is very exciting, GAA for example.1 NeoMOS is agnostic to device architecture as long as it is a field effect transistor so it is applicable to planar CMOS, FinFET as well as Gate-All-Around.”
However, real deployment on a large scale requires more than a demonstration but meeting process-voltage-temperature (PVT) requirements as well as reliability. Processor aging is an important factor for data centers for example.
“The semiconductors industry will not rest. There was some supply hiccup during the past two years of chip shortage and it seems that we are entering into some excess manufacturing capacity now but it these are stimulating factors for semiconductors innovation,” concludes Messica.