As Moore's Law is again reaching its limits, several technologies, specifically chiplets, could be the key to extending it for many more years.
As Moore’s Law is again reaching its limits, several technologies, specifically Chiplets, could be the key to extending it for many more years.
Moore’s Law, named after former Intel Corp. CEO Gordon Moore, states that the number of transistors in an integrated circuit doubles every two years. The prediction is widely used in the semiconductor industry, especially for microprocessors. Manufacturers use the “law” to set roadmaps and R&D targets.
Obviously, to continue this increasing density and miniaturization of semiconductors, many new technologies have appeared in the 55 years since Moore’s Law was first proposed.
Integration, especially for technologies such as System on a Chip (SoC) made it possible to combine several different components. SoCs enable faster communication between the parts, lower power consumption, improve optimization of wafer surface, reduce board real estate use, and lower costs.
Chiplets could add another step of performance extending Moore’s Law
Recently, at TSMC’s 2021 Open Innovation Platform, James Huang, Vice President of R&D, Alchip Technologies, argued that chiplets and advanced packaging provides competitive cost structure versus monolith SoCs while maintaining comparable performance and power consumption.
Huang cited two pieces of technology that will be critical to chiplet / packaging developments: One is TSMC’s 3DFabric and CoWos combined technologies. The other is Alchip’s APLink die-to-die (D2D) I/0.
Chiplets refer to the independent constituents which make up a large chip built out of multiple smaller dies. The increased cost of manufacturing on leading-edge process nodes is producing a reversal on the SoC integration trend. It is now becoming more advantageous to separate components into smaller “chiplets” to improve yield on each wafer.
In order to keep Moore’s law predictions valid, chiplets need to provide similar performance as SoCs.
AIchip’s APLink D2D I/0 enables high-speed data traffic between multiple chiplets. APlink 1.0, targeting TSMC 12nm process, and APlink 2.0, targeting 7nm process, feature line rates of 1Gbps and 4Gbps, respectively.
APLink 3.0 is currently undergoing test chip results evaluation, having achieved its target line rate of 16Gbps.
James Huang gave the audience a glimpse of the company’s roadmap when he mentioned the upcoming APLink 4.0, targeting the 3nm D2D manufacturing process.
The APlink 4.0 IP will support both north/south and east/west orientations and symmetric PHY alignment to minimize D2D wire length. Its interconnect topology will feature a Source-synchronous I/O bus running with standard core voltage. The IP will run at 12Tbps per PHY macro, with speeds of up to 16 Gbps per DQ line with only five nanoseconds of latency. Taken together, this will result in reliable system operations.
The key to bringing the future of chiplet and advanced packaging to reality is Alchip’s flexible business model that allows the company to engage at one of three points in the design chain. Such flexibility maximizes both internal engineering expertise and ASIC design compatibility.
“But what makes this even more aligned with the needs of future technology innovation is a flexible business model that brings the future to reality,” Huang pointed out.
For more information, go to www.alchip.com.