Microsoft Taps Cadence for RAMP Phase II Program

Article By : Cadence Design Systems Inc.

Cadence was selected to participate in the Microsoft Rapid Assured Microelectronics Prototypes (RAMP) Phase II initiative.

Cadence Design Systems Inc. was selected to participate in the Microsoft Rapid Assured Microelectronics Prototypes (RAMP) Phase II initiative.

The RAMP program is an initiative within the Department of Defense (DoD) that NSWC Crane facilitates through the Strategic & Spectrum Missions Advanced Resilient Trusted Systems (S2MARTS) Other Transaction Authority (OTA) powered by National Security Technology Accelerator (NSTXL). The initiative focuses on the advancement of State-of-the-Art (SOTA), secure microelectronics design methods.

As part of the Phase II program, Cadence is providing best practice recommendations and security integrations with its digital and verification design flows for advanced system-on-chip (SoC) designs from select defense industrial base prototype designs. The plan is to have the secure design environment integrated into the Microsoft Azure-based deployment infrastructure to support state-of-the-art microelectronics development for mission-critical aerospace and defense applications.

The RAMP program focuses on utilizing commercial best practices to establish design requirements for new and emerging government application areas, including 5G and artificial intelligence (AI). Cadence is participating in multiple tasks associated with this initiative, including applying its leading commercial solutions to the secure chip design, test, and verification process to ensure it is seamless.

“Accelerating the development cycle for advanced silicon with first-pass success is essential for driving secure microelectronics innovation,” said Nimish Modi, Senior Vice President, Marketing and Business Development, Cadence. “With our continued focus on developing the most advanced computational software solutions, Cadence is well-positioned to deliver a rapid and effective design flow between the front-end design capture and verification phase to the implementation of secure silicon devices.”

“Cadence’s participation in the RAMP program brings performance-optimized flows for the DoD’s use on Microsoft Azure,” said Mujtaba Hamid, General Manager, Silicon, Modeling and Simulation, Microsoft. “With this, we established a more comprehensive EDA design environment for the development of advanced microelectronics to facilitate the delivery of new aerospace and defense applications securely and efficiently.”

Both the digital full flow and verification full flow offerings support the aerospace and defense industry and align with Cadence’s broader Intelligent System Design strategy.

 

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