Marvell Joins TSMC’s Upper Echelon Customers of 5nm Chips

Article By : Alan Patterson

Marvell is filling the void where HiSilicon used to be, both in the market and at TSMC...

Marvell, after reinventing itself as a supplier of data infrastructure silicon, has joined the upper echelon of Taiwan Semiconductor Manufacturing Co. (TSMC) customers by winning capacity allocation at the 5nm node.

Marvell and TSMC said they will deliver a comprehensive silicon portfolio using the world’s most advanced process technology, which is now entering production. The partners are aiming for the more-than-Moore era with die shrinks to 5nm from 7nm and packaging innovations that boost the density of storage, bandwidth, speed and machine-learning capabilities while cutting power consumption.

Marvell updated its logo earlier this year.

“We’ve been able to achieve on average 40 percent lower power for a given design point and performance point,” Marvell ASIC Unit general manager Kevin O’Buckley said in an interview with EE Times. “We’ve been able to achieve 40 percent greater integration, mostly measured as die area shrink, which can be used either to pack in more performance in a given die area or in some cases, lower costs.”

One of the fastest growing parts of the infrastructure semiconductor market is in switching and custom-built accelerator products as cloud-data hyperscaler companies like Microsoft and Google aim to move workloads that are running on general-purpose compute devices like CPUs and GPUs into custom silicon “because they own the whole stack from software all the way to the transistors,” O’Buckley said.

With multiple designs under contract for its 5nm portfolio, Marvell is developing solutions across a range of markets with first products sampling by the end of next year.

Marvell sees growth potential in 5G despite losing the Huawei business more than a year ago when the US government blacklisted the Chinese company. Marvell counts Nokia, Ericsson and Samsung among its 5G infrastructure customers.

TSMC needs big-league customers to fill a gap left by Huawei’s HiSilicon chip-design unit, which earlier

this year accounted for about 14 percent of sales revenue at the world’s biggest semiconductor foundry. HiSilicon used TSMC’s 7nm process technology to make its Kirin processors.

TSMC’s largest customers currently include Apple, AMD, MediaTek and Qualcomm.

Core businesses

Marvell sees three areas — 5G infrastructure, enterprise networking, and cloud data centers — as its core businesses. In the future, Marvell expects automobiles to be another growth driver.

O’Buckley used Marvell’s Octeon product line as an example of how TSMC’s 5nm node can help create new applications for embedded infrastructure in a range of wired and wireless networking equipment including switches, routers, secure gateways, firewalls and network monitoring solutions.

“In advanced technology, the capability of our Octeon platforms moves to higher performance capability while preserving the key power envelope for things fitting on a PCI card,” O’Buckley said. “We’ve been able to push that application viability to things like 5G carriers where they have much more aggressive power-envelope requirements and frankly more stringent cost targets than some enterprise applications.”

Marvell says Octeon is the world’s most widely deployed data processing unit (DPU) for data-center scale computing that enables acceleration and offload capabilities, including Smart NICs and security accelerators.

Machine learning

Marvell says machine learning accelerators are another example of why it’s critical to migrate to 5nm from 7nm.

“A lot of folks building a world-class machine learning accelerator would not even be able to fit all the content in the reticle with a 7nm design,” Marvell Integrated Systems Technical Director Mark Kuemerle told EE Times.

Block diagram of Marvell’s Octeon.

The company is working with TSMC on chiplets designed for low power consumption with efficient interconnect between different die. Marvell is creating scalable systems for machine learning accelerators and data centers by to moving to 5nm, he said.

“The barrier to entry for a lot of high-end switching applications is being able to fit all the content onto a single reticle,” Kuemerle said. “Interface chiplets are a critical part of the strategy to scaling content. We can use these die-to-die interconnect topologies to build a scalable system so a customer doesn’t need to make multiple products to fit each part of their market.”

Growing ASIC business

Marvell expects more of its sales to come from ASIC design.

Customers can contribute to the design, Marvell CEO Matt Murphy said in a May 2 conference call with analysts. “We stitch it together. We can do it very quickly without the customer having to hire a gigantic design team and take three years.”

If customers have a vision for a product and an implementation that’s not perfectly aligned with Marvell’s standard products, the company will develop ASICs for system integration into a single module, according to O’Buckley. Customers may also want to modify Marvell’s standard products through customization with their IP as an alternative to a full-custom ASIC build, he said.

“A very real portion of our revenue portfolio today comes from customized products. I would say north of single digits,” O’Buckley said. “However, the directional profile is for increasing that share over time.”

A major driver of that is hyperscaler customers that have the ability to make investments in products that support their implementation needs, he said.

Behind Marvell’s 5nm solution set is the company’s IP portfolio that covers infrastructure requirements including high-speed SerDes up to 112Gbps long-reach processor subsystems, encryption engines, system-on-chip fabrics, chip-to-chip interconnects and a variety of physical layer interfaces. These technologies are in development on TSMC’s 5nm process.

Foundry partners

Marvell’s recent acquisitions include foundry partnerships with companies such as Samsung and GlobalFoundries. Marvell expects those partnerships to shrink in the future.

“We are buying wafers at some legacy nodes like 14nm and 28nm from foundry companies that simply are not making the investment in 7nm and beyond,” O’Buckley said. A consolidation at the advanced nodes will concentrate those partnerships away from what was a more diverse group, he said.

TSMC endorsed its alliance with Marvell.

“We are proud to partner with Marvell to serve the data infrastructure market with cutting-edge silicon and are committed to supporting their growing needs in development, quality, supply and capacity,” Kevin Zhang, senior vice president of business development at TSMC, said in a press statement. “In the 5G era, more applications than ever are demanding the most advanced silicon technology we can provide. We look forward to collaborating with Marvell to meet these demands with our combined design and process expertise and extend our long history of partnership to the 5nm generation and beyond.”

Marvell teams are working with TSMC on development at the 3nm node to ensure that the company is positioned to develop products in the next few years, O’Buckley said.

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