A Marriage of IC Security with System-Level Synthesis

Article By : George Leopold

A new U.S. design initiative would help silicon architects achieve system-level synthesis while incorporating security into the design process...

System-level synthesis has long been a goal of chip designers, allowing them to focus on full-blown IC designs rather than taking a block-by-block approach. A new U.S. design automation initiative would help silicon architects achieve that goal while also incorporating security into the design process without exacting penalties for constraints like power or performance.

The Defense Advanced Research Projects Agency (DARPA) announced a pair of teams last week to ramp up its secure chip design initiative. The year-old Automatic Implementation of Secure Silicon (AISS) program also would help silicon architectures specify performance constraints while automating the design-in of defenses that would secure an entire device lifecycle.

“We can kill two birds with one stone,” said Serge Leef, DARPA’s AISS program manager, of achieving the long-sought goal of system synthesis while embedding security into the IC design process.

The pursuit of system synthesis has proven expensive, both in terms of development costs as well as the design penalties exacted for performance and supply chain considerations like preventing reverse engineering. Leef added in an interview that AISS also seeks to address the relative lack of security expertise among hardware designers as well as current synthesis approaches, which Leef described as “rigid.”

This one-size-fits-all approach proves inflexible across a range of applications. For example, power, performance, size and supply chain parameters for a consumer product would vary greatly from those required for a weapon. Design considerations for a guided missile would be overkill in a 200,000-gate consumer device.

Hence, AISS seeks to automate the design process based on the requirements of specific applications. The result would be an optimized architecture while reducing cost and, therefore, improving overall design economics.

As semiconductors emerge as a choke point in frayed U.S.-China trade relations, the chip design initiative ultimately seeks to address the tradeoffs designers must make between chip economics and security. Another benefit would be greater IC design productivity, DARPA said.

The four-year, $75 million AISS program also would enable silicon architects to set parameters for chip constraints like power consumption and performance, then factor in security. The automated process would then produce a secure architecture tuned to an application.

In the process, Leef emphasized, chip security becomes a design priority on the same level with power, performance, size and supply chain parameters.

He likened the AISS framework to the addition of fluoride to water supplies beginning in the 1950s. Despite unfounded conspiracy theories, fluoride at appropriate levels is widely recognized as beneficial for teeth. When it became clear that consumers would not take tablets, fluoride was eventually added to public water supplies.

AISS does for chip and supply chain security what fluoride did for a dental health. “Security is integrated into the design flow” from the start, Leef said.

Chip tracking technologies like “infinite tracing” have emerged in recent months as the U.S. seeks to block Chinese access to advanced chip-making equipment. The AISS program uses an emerging security framework called PUF, physical unclonable feature. The device-level approach exploits inherent randomness introduced during manufacturing to give each chip a unique identifier.

Secured chips could then be tracked from conception, design and deployment and throughout their lifecycles via passive or active tags, the latter including built-in memory for storing cryptographic keys. The DARPA framework would assign a unique ID for each AISS-design chip, akin to a unique human fingerprint.

The agency’s approach represents a fundamental shift in chip design. Until now, security tended to be a “higher layer software problem,” said Daniel Cooley, chief strategy officer at Silicon Labs. “But it’s now working its way down deep into the technology stack to the foundries. Actually, things are happening at the foundries, chip design houses, and [at] every level of the technology stack.”

AISS is part of that secure hardware push. While focused on Arm-based architectures, other secure design efforts are focuses on RISC-V and other emerging architectures, industry sources said.

The three-phase DARPA program will move from a generic SoC design incorporating the AISS security engine to what is hoped will be a marrying of system synthesis and baked-in chip security that would allow for tracking devices throughout their lifecycle.

A team led by EDA vendor Synopsys will focus on both system synthesis and design security. The team includes Arm and U.K.-based embedded analytics vendor UltraSoC, each of which will contributed semiconductor IP to the effort.

UltraSoC’s framework is embedded in chips to perform analytics on chip operations, sounding an alarm when it detects suspicious behavior. The approach complements security techniques like Arm’s TrustZone. “That is a lock, we are the burglar alarm,” said UltraSoC CEO Rupert Baines,

The results of the three-phase AISS program will be released “incrementally,” Leef said, so chip designers could eventually embed security into complete device designs up to several hundreds of thousands of gates.

Leave a comment