Reduce dynamic power by "tens of %" and static power by “order of magnitude”...
Power reduction methods for Integrated circuit design, especially for the battery driven mobile devices, such as tablets, mobile phones, wearable devices, IoT devices etc., are crucial for the future electronic products.
Power consumption becomes increasingly important for electronic system. In view of this, IC developers focus on ultra low power design by reducing dynamic and static power consumption.
(A) Adopt low-power/low leakage wafer process technologies
Wafer fabs offer Low-Power (LP) and Low-Leakage (LL) processes with LP and LL devices. Adoption of LP and/or LL transistors is able to reduce circuit’s power consumption straightly. For example, TSMC 22ULL, 40ULP, 55ULP, etc.
(B) Reduce operating voltage
Power= Voltage x Current, lowering operating voltage reduces power dissipation directly. However, consideration of design and process variation is required.
(C) Clock Gating approach
Clock gating approach saves power by adding additional logic cells in the design to optimize the clock tree structure. In general, a clock signal connects to many flip flops, lots of the flip flops retain previous clock value. Switching off the clock signal to these flip flops which still retain previous values results in less toggling of the clock path, thus saves dynamic power.
Clock Gating Cell
(D) Power Gating approach
Power Gating approach is a way of power reduction by shutting off the current to the circuitries that are not in use. Some circuitries in a chip design are not always actively used. Turning off the power of these circuitries enables lots of saving of static (leakage) power and some dynamic power, even clock is switched off.
(a) ISO cell (b) RISO cells, act like a buffer with enable.
(E) Multiple Voltage and Frequency Domains
Multiple voltage and frequency domains also can save power. For a high-performance design circuitry, it requires higher voltage supplies to generate high frequencies. Once the signal reduces frequencies, it then no more need for high voltages. When the signals cross the different voltage domains, a level shifter can be used to reduce the total power.
Illustration of Level Shifter between Power Domains
(F) State Retention Power Gating approach
For register data that may get lost in power gating requires a “power-on-reset”.
While the circuitry stays at stand-by mode, State Retention Power Gating can trade off power dissipation to retain some registers’ state values in exchange of more efficient wake-up and operates at a known state.
Header cell and retention flip-flop, integration of the header cell and the retention flip-flop
M31’s IP portfolio for low-power design include SRAM, Standard Cell Library, Analog IP, and USB PHY is described below
Leverage Monte Carlo Method to perform simulations. Provide analysis on SRAM by following wafer fabs’ process technologies. Identify the electrical characteristics and distributions that affect SRAM’s quality and yield. These will get optimized design solutions.
(B) Standard Cell Library
i. Power management kit contains
ii. Low Power Optimization Kit contains
iii. Low dynamic power strategy
With implementation of low-power cell library solutions, the total power of the design block can be reduced by around 10%.
iv. Ultra-Low leakage Library contains
This figure shows a benchmark data by targeting TSMC 40ULP process node. It shows that M31 TGO cell library reduces 70% power dissipation in comparison with core device cell library under low operation frequency (below 1MHz).
(C) Analog IP
To get an IC design with better Power (P), Performance (P) and Area (A), M31 proposes the “Modular IP” concept in designing data converters (ADCs/DACs) and analog-frond-ends (AFEs).
i. ULP ADCs/AFEs
ULP ADCs are designed with high configurability so that they are capable of retrieving both kinds of input signal: voltage or current sent by the transducer or the very first front-ends. For specific application, some ADCs feature built-in (or inherent) anti-aliasing filters as well as programmable gain adjustments (PGA) to relax the design effort of preceding stages. Highlighted features are:
ii. High Performance Data Converters
As the data rate and signal bandwidth continue to be increased toward GHz or MHz, the operating clock/bandwidth of the data converters must be capable of handling massive amounts of data. To achieve such requirement, M31 proposes advanced data converter architectures including Continuous-Time (CT), Discrete-Time (DT) or Hybrid Delta-Sigma ADCs/DACs with the following applications::
Lowering supply voltage is a quick and easy solution to reduce power consumption; however, it requires to implement variation-aware technique, such as PVT sensors, to prevent failure since transistors are sensitive to process (P), voltage (V), and temperature (T) under low voltage operation. Therefore, M31 proposes PVT sensors with medium-to-high performance and ultra-low power (ULP). Furthermore, by integrating analog interface (TIA, PGA, and Filter, etc.) as well as ADC (“Modular ADC” based design), these PVT sensors become smart. Also, PVT sensor IPs assist in accelerating time-to-market of feature-rich SoC design.
Ultra-Low Power Fractional PLL is a general purpose frequency synthesizer with input reference frequency range from 10 to 240 MHz and 3:1 output frequency range. The PLL IP is a typical Type-II PLL. The fractional part of the output frequency is achieved by using a programmable 3rd-ord sigma delta modulator. The PLL IP operates on core supply voltage with embedded LDO for excellent supply rejection in noisy SoC applications. It is designed with easy usage and simple integration without complex configurations. Furthermore, this IP offers a reliable clock source for SoC that operates under a very low voltage（0.7V）to save power.
(D) USB PHY
M31 has the worldwide smallest Low-Power USB PHY 2.0 that targets portable devices and IoT applications. It reduces more than 30% operating current and 70% stand-by current. M31 offers a next generation USB 2.0 IP which delivers an extremely smaller die area and lower active and suspend power consumption. M31 leverages a new design architecture to implement USB 2.0 IP without sacrificing USB 2.0 performance. The USB 2.0 IP is not only suitable for USB peripherals but also is an optimized solution for SOC with multiple USB ports.
In addition, M31’s Crystal Free Technology allows USB PHY to operate without external crystal oscillator nor input reference clock. It is named as BCK (Built-in-Clock) USB PHY. This BCK USB performs background calibration during USB data transfer to ensure the internal clock frequency accuracy. The IP meets IF-compliance specification and it performs same electrical characteristics and low power as the standard USB PHY.
Eye Diagram of USB 2.0 PHY
A Table of Availability in summary is provided as below. Please refer to the latest M31’s IP catalog for more details.
|M31 Technology Corporation
14F, No.1, Taiyuan 1st St., Zhubei City,
Hsinchu County 30265, Taiwan
|M31 USA Office
1900 McCarthy Blvd., Suite 105,
Milpitas, CA 95035
About M31 Technology
M31 Technology Corporation is a professional Silicon Intellectual Property (IP) provider. The company was founded in October, 2011 with its headquarters in Hsinchu, Taiwan. M31’s strengths are its outstanding R&D capability and customer services. With substantial experiences in IP development, IC design, and design automation fields, M31 focuses on providing High-speed Interface IP such as SerDes, USB, PCIe, MIPI, SATA, and Foundation IP such as Standard Cell Library, Memory Compiler, and ESD/IO Library solutions. The vision of M31 is being the most trustworthy IP provider in semiconductor industry. For more information please visit https://www.m31tech.com