Lattice Expands Into Mid-range FPGAs

Article By : Sally Ward-Foxton

Lattice is entering the mid-range FPGA market with its Avant platform.

Lattice Semiconductor, previously known for its small, low-power FPGAs, is entering the mid-range FPGA market in a move that will double the company’s addressable market to approximately $6 billion.

Lattice Avant Chip
Lattice’s Avant platform is designed for FPGAs up to 500k logic cells (Source: Lattice Semiconductor)

Lattice has announced a new technology platform for its mid-range FPGA products, Avant, and the first series of mid-range FPGAs to be built on this platform, the Avant-E series, with up to 500 thousand logic cells.

“When we were concepting Avant, we went out and talked to over 100 customers worldwide, in all geographies, in all of our major verticals, to understand what it is they were looking for,” Jay Aggarwal, director of silicon product marketing at Lattice, told EE Times. “What we heard from them was resounding—they’re looking for innovation in the mid-range space, because the mid-range FPGA space has been overlooked by our competition, who’ve focused on their high-end devices.”

Aggarwal characterized competitors’ existing mid-range offerings as primarily being cut-down versions of higher-end FPGAs, with resulting architectural baggage.

“Customers are looking for innovation [in the mid-range space], not just in power and performance, but in size too,” he said.

Lattice is banking on carrying over experience with smaller FPGAs to produce something that can compete in the computing, communications, industrial, and automotive markets.

Nexus and Avant

Lattice introduced the concept of technology platforms in 2019 with Nexus, on which the company has since built five product families. The platform concept allows design reuse and lowers development cost, helping the company increase its product cadence. This approach drove revenues from $97 million in Q1’20 to $172 million in Q3’22.

Where Nexus focuses on smaller FPGAs below 100 thousand logic cells, Avant will cover devices between 100-500 thousand logic cells. The new platform features architectural advantages and new capabilities to address an expanded set of applications. While Nexus was built on 28-nm FD-SOI at Samsung Foundry, Avant will use TSMC’s 16-nm FinFET process.

Compared to the largest Nexus device, Avant devices can be 5× bigger, with 10× more serial bandwidth and will offer as much as 30× the AI performance, according to Lattice. Avant platform devices will feature configurable SERDES up to 25 Gbps, hardened support for PCIe Gen4, and high-speed memory interfaces for LPDDR4 and DDR5 based on customer feedback.

Avant devices will also feature a new post-quantum ready security engine that supports advanced cryptographic algorithms—a feature Lattice has identified as very desirable for all customers, regardless of industry sector.

Avant devices will be able to use existing software stacks from the Lattice portfolio, including Lattice’s solution stacks for edge AI, embedded vision, security, factory automation, and ORAN infrastructure. This includes reference designs, SDKs, design tools, and IP. Design software, including Lattice Propel for SoC designs and the Lattice Radiant IDE, will also be compatible with Avant devices, Aggarwal said.

This will help enable straightforward migration of larger applications from Nexus to Avant devices.

“Ninety percent of customers we’re targeting are existing Lattice customers, so it really is about scaling with our customers and giving them more capability, while making it easier for them by using the same solution stacks and the same tools with new levels of efficiency and ease of use,” said Matt Dobrodziej, VP of segment marketing and business development at Lattice, adding that most of Avant’s target market will be moving deeper into existing customers’ applications to enable new capabilities.

Edge AI

AI inference at the edge is a key driver for new mid-range FPGAs based on the Lattice Avant platform. To handle AI workloads efficiently, Avant’s programmable fabric is mixed with power-optimized embedded memory and DSP capabilities.

Why not harden something more AI-specific than DSP capabilities as part of the architecture?

“If you look at other devices targeting AI, we’ve heard from our customers that those devices with specific AI blocks quickly become out of date, so they are dedicating a lot of silicon to things that don’t have the longevity we’re looking for,” Dobrodziej said. “By keeping a rich mix of resources and a highly optimized fabric for AI, we can achieve a lot of the things you’d expect from some of these hardened blocks in our fabric. The value of flexibility is much higher right now with our customers.”

Lattice Avant compute element
The Lattice Avant programmable fabric also includes embedded memory and DSP capabilities tuned for AI workloads (Source: Lattice Semiconductor)

Avant devices will power AI with faster performance and higher image resolution in factory fault detection, 3D depth detection in robotics, and automotive in-cabin occupant monitoring.

Over and above specialized ASICs for AI at the edge, Dobrodziej and Aggarwal said that FPGAs offer several advantages, mainly surrounding flexibility.

“What we found talking to customers is that… there can be other processing and pre-processing functions in that pipeline that will dictate the performance and the ultimate end user experience,” Dobrodziej said. “We still feel the most important aspect to deliver to those applications is the flexibility to work with any sensor, to be able to do pre-processing that not only better matches the correlation of the training dataset to what the sensor is seeing, but also being able to do the types of pre-processing that makes the downstream metadata a lot better.”

“One thing you use FPGAs for is where you have evolving standards, so flexibility is the key,” Aggarwal added. “As soon as you lock yourself into a specific architecture or solution, more than likely [the workload] is going to move past you and now all of a sudden you have to redesign. We’ve been able to continually improve on algorithms on our devices and provide a higher level of performance out of the same FPGA.”

First family

The first family of Avant-based devices is the Avant-E family. The first device in this family will be the largest at 500 thousand logic cells in a 13 by 15-mm package, intended for data processing and edge AI applications. Three hundred and 200 thousand logic cell-devices will follow in 2023. Compared to competing devices (Intel Arria V GZ (450 thousand logic cells) and AMD Kintex 7 (478 thousand logic cells)), this 500 thousand logic cell FPGA will be 2.5× more power efficient, with up to double the throughput and up to 6× smaller, according to Lattice’s comparisons.

Further Avant product introductions are expected in 2024. Lattice will also continue to invest in its Nexus platform, releasing a further two Nexus families in 2023 and more in 2024. Also coming in 2023 is the company’s first developer conference.

The first Lattice Avant-E FPGAs are shipping now.

 

This article was originally published on EE Times.

Sally Ward-Foxton covers AI technology and related issues for EETimes.com and all aspects of the European industry for EETimes Europe magazine. Sally has spent more than 15 years writing about the electronics industry from London, UK. She has written for Electronic Design, ECN, Electronic Specifier: Design, Components in Electronics, and many more. She holds a Masters’ degree in Electrical and Electronic Engineering from the University of Cambridge.

 

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