Keysight's 120GBd BERT solution validates next-gen chip deployments of up to 120GBd for the 1.6T market with unachieved signal integrity.
Keysight Technologies Inc. has introduced a new 120GBd High-Performance Bit Error Ratio Test (BERT) solution (M8050A) for validating next generation chip deployments of up to 120GBd for 1.6T (or one trillion bits per second) market with unachieved signal integrity.
Digital development and senior validation engineers are challenged with higher loss and distortions when moving from 112Gbps per lane to 224Gbps per lane. The new M8050A is designed to overcome these challenges with high signal integrity enabling more test margin. This allows customers to move to next generation 1.6T designs while maintaining the flexibility needed to quickly adopt the M8050A to new requirements in the future.
Keysight’s new M8050A BERT delivers application-specific integrated circuit (ASIC) technology designed by Keysight to optimize the design to the requirements of the instrument. This offers the following key customer benefits:
“From fully automated dark factories, closed loop digital twins to the metaverse, today’s applications and services generate vast amounts of artificial intelligence workloads. New electrical and optical designs are required to handle these workloads and make progress towards sustainability, achieving climate goals,” said Dr. Joachim Peerlings, vice president and general manager of Keysight’s Network and Data Center business. “We are pleased with Keysight’s continuous efforts to deliver first-to-market solutions that support our customers in achieving these goals.”
Simplified, time-efficient testing is essential when developing next-generation computer, consumer, or communication devices. The Keysight M8000 Series is a highly integrated bit error ratio (BER) test solution for physical layer characterization, validation, and compliance testing. With support for a wide range of data rates and standards, the M8000 Series provides accurate, reliable results that accelerate your insight into the performance margins of high-speed digital devices.