ISSCC: Roadmap on 3D Interconnect Density

Article By : Don Scansen

The common theme coming out of the chiplet forum at ISSCC was the need for a 3D interconnect density roadmap.

A lot has been said about the shift from a system-on-chip integration of functionality to a technology integrating each IP block as a physically distinct chiplet. Perhaps the emergence of this new paradigm is most aptly represented by the devotion of a full forum session to chiplets at the International Solid-State Circuits Conference. The virtual conference just wrapped up.

All eight of the forum (aka ISSCC Exploration) presentations offered an interesting look at chiplet technology. But three in particular provided an overview of the systems already on the market, the technology trends, and the ecosystem necessary to accelerate the new design approach.

AMD, Getting Started

AMD’s latest crop of microprocessors are well-known for their chiplet approach that optimized design and use of the most appropriate technology node for the chips. AMD senior vice president, corporate Fellow, and product technology architect Sam Naffziger presented the details of the motivations (wafer manufacturing technology slowing) and the challenges of breaking up their processors into purpose-built slices better matched to cutting edge and older technology nodes. The case study was the development of the EPYC server processor.

Naffziger pointed out that the idea of circuits comprised of multiple chips isn’t new. The multi-chip module (MCM) idea started back in the days of ceramic substrates and migrated to organic substrates. “The end of Moore’s Law plus packaging advancements create a new era for multi-chip/chiplet approaches.”

The big selling point for chiplets as far as AMD is concerned appears to be improving the cost per good die. Higher yields are a natural benefit of smaller chip sizes, so each wafer AMD buys from the foundry ends up with fewer failing die. Since a defect anywhere on a big die can kill it, partitioning into four, for example, would still net you three quarters of a shippable product as opposed to none with the bigger chip size.

Naffziger described the challenges and solutions in terms of a case study using the EPYC server processor. A natural inclination might be to think that a high price would be paid in additional silicon area moving from a monolithic design to the MCM especially for a first-generation design.

AMD lowered the cost of the 1st generation EPYC chip by partitioning the design into chiplets (source: ISSCC 2021)

Not so. AMD calculated an additional 10% of silicon real estate required for the die-to-die communication blocks, redundant logic and other unnamed add-ons to enable the chiplet design compared to a hypothetical monolithic EPYC chip. The total die cost of the multiple chiplets saved 41% compared to AMD internal estimates for the monolithic processor.

Shedding over 40% of silicon costs would seem like a tough act to follow, so what did second generation EPYC products achieve?

Upping the Ante
Much has been made of Moore’s Law slowing, but AMD and other high performance computing (HPC) companies also recognized that leadership requires use of cutting edge process technology. But the cost of the latest manufacturing nodes has become a serious issue. The trend ticks up dramatically beyond 14/16 nm.

AMD calculated wafer cost per area of good die (source: ISSCC 2021)

Fortunately, the chiplet solution provides optimized cost and performance. For EPYC, AMD partitioned the design to put the CPU functions that would benefit most from the next node (7nm) while leaving analog and I/O blocks for a less advanced technology. It all makes perfect sense. The analog circuits simply do not benefit from scaling transistors or interconnect pitches. It is even more striking to consider the I/O themselves with bump pitches for getting signals off chip scaling very slowly compared to the digital circuits.

The second generation EPYC compute complex die (CCD) is 86% committed to CPU and L3 SRAM memory. That seems very effective use of the more expensive 7nm technology.

The analog and I/O are a significant portion of high-performance desktop and server processor designs. This is quite apparent looking at shots of the EPYC 2 products with the quite large I/O die (IOD). The data input and output of these chips accommodates a lot of serial data like PCIe (128 lanes on EPYC 2) and DDR channels.

AMD EPYC chiplet evolution (source: ISSCC 2021)

Slicing the silicon pie was only the first part of the problem. The chiplets solved one problem but created new design challenges. Connecting nine chiplets on one package substrate took serious engineering.

But the work to push EPYC 2 into the realm of a true mix-and-match chiplet design had its payoff. AMD calculates lower costs for the design with separate IOD on the cheaper 14nm technology over the full product range of core count and performance. Costs are halved versus monolithic processors with 24 to 48 cores. AMD notes that larger cores are not even feasible as a monolithic product. Judging these results, there really was no alternative. Chiplets were the way forward.

Looking ahead, Naffziger sees a few possibilities like reduced connection overhead with interposers and denser interconnect, stacking memory directly on the compute die, and true 3D stacking beyond just memory die.

The Foundry Story
Until there is a complete and open ecosystem, chiplets will remain just for a few top players. The foundry will play a central role. What does TSMC have planned? The ISSCC chiplet forum heard straight from TSMC R&D Vice President and distinguished fellow, Douglas Yu.

First, let’s check a couple of definitions for those like myself who struggle with the lingo. You may have seen or heard the terms MM or MTM. “MM” is not a candy although it was just as tasty to the semiconductor industry for half a century. Rather than a candy coated chocolate, that’s More Moore to those outside the loop. Naturally, one need only add a “T” to arrive at “MTM or More than Moore.

TSMC suggests three directions to continued semiconductor innovation, ideally working together (source: ISSCC 2021)

MM and MTM are at times independent branches of technological advancement and scaling for semiconductor products. As a foundry and one that has developed a keen interest in advanced packaging as well, it is no surprise that TSMC strongly believes in combining MM and MTM to deliver the most advanced chips possible.

In the MM category, Yu’s presentation mentioned several key drivers of the chiplet approach, HPC die sizes, I/O scaling out of sync with digital logic, and IP re-use and acceleration of product schedules. This last point is a key one. Partioning of functionality into chiplets allows each specialist design team to keep its own best development schedule.

But for chiplets, the focus is on MTM. TSMC has been heavily invlolved in advanced packaging for quite some time. Their InFO branded integrated fan-out wafer-level package technology was a game-changing technology for mobile devices when Apple adopted it for their A10application processor in 2016.

TSMC looks to pull their frontend chip stacking technology and backend packaging technologies together into a new system-level integration program they are trademarking as 3DFabric. In the front end, TSMC provides chip-on-wafer (CoW) and wafer-on-wafer (WoW) Together, these are system-on-integrated-chips or SoIC. With CoW and WoW, maybe we could have Wagyu.

TSMC SoIC provides better interconnect performance for 3D integration (source: ISSCC 2021)

On the packaging and assembly front, the TSMC technologies are CoWoS and the aforementioned InFO. CoWoS for us slow learners is chip-on-wafer-on-substrate.

At the risk of sounding like an old man longing for the good old days, I need to point out a couple of acronyms that TSMC has co-opted for the 3D system integration age. You already met the first one. SOIC used to be a small outline integrated circuit. For those of us who might still have old textbooks so titled, TSMC has also replaced our understanding of LSI. Henceforth, this will be local silicon interconnect. Anything else is just so pre-pandemic.

By the way, TSMC’s LSI is similar to the Intel’s EMIB or Embedded Multi-die Interconnect Bridge. Even silicon interposers appear to function better as chiplets. The TSMC SoIC is bonded, so it also gives a 16X improvement over µbump.

It might seem like a little piling on TSMC and their acronym use, so I will point out one not of their making. Thinking back to the AMD talk, we now have CCD meaning compute complex die rather than the age-old charge-coupled device. (Stay tuned for details on how to pre-order my book discussing the acronym apocalypse.)

TSMC’s contribution to the chiplet forum ended with a view of the 3DID (3D interconnect density) roadmap for future integration. The charts give a stark contrast of how silicon scaling has flattened while 3D approaches, particularly SoIC from TSMC, are in a golden age of doubling every two years.

TSMC projects a two-year cadence for doubling interconnect density, 3DID (source: ISSCC 2021)

If you feel overwhelmed with the terminology, the acronyms, or both, that’s actually a good thing. It shows that there are a lot of options and flexibility that’s getting the chiplet age off to a good start. TSMC will have a lead role in the direction chiplets take in the future. The ISSCC 2021 innovation forum given by TSMC’s Yu provided insight into how that role will be played.

Imec, R&D view
Considering the interconnect density (don’t forget – 3DID) roadmap that TSMC presented, it is useful to take a closer look at a few of the technology pieces that will enable the rapid progress predicted.

Eric Beyne is director of Imec 3D System Integration Technology Program as well as a senior fellow and vice president of R&D. Beyne is well-known in 3D integration circles, and this forum took a deep dive into three major technology areas that will determine the future of 3D integration.

Imec offered their roadmap for 3D interconnects (source: ISSCC 2021)

Looking at the interconnect landscape, 3D interconnects cover the range from just under a millimeter for stacked packages (like PoP or package-on-package) to less than 100nm for true 3D-IC technologies using transistor stacking. With the latter, the density exceeds 108 / mm2. In other words, there is a lot of room to improve upon the typical production technologies of today.

In the Imec view, there are three key technology elements for 3D integration:

  • Through-silicon-via (TSV)
  • Die-to-die, die-to-wafer stacking & interconnect
  • Wafer-to-wafer bonding & interconnect technology.

According to Beyne, research is showing good promise for scaling TSV’s. However, vias in commercial products have remained static. The problem is the “interconnect gap.” The microbump has not caught up to the point where the TSV can be fully utilized. More aggressive scaling is necessary.

Imec suggests that very aggressive µbump scaling to match TSV density is possible (source: ISSCC 2021)

Teams at Imec have been working on improving bump density. Beyne showed solder bump pitches down to 7µm with thermocompression bonding. The SEM images showed a technology demonstrator with four stacked die with 7µm pitch TSV bumped and interconnected. Clearly, Imec wants industry to realize the opportunities and get microbumps up to speed with TSV technology.

The common theme coming out of the chiplet forum was the need for a 3D interconnect density roadmap. (Don’t forget the acronym – 3DID.) Just like those old roadmaps for scaling planar CMOS transistors, the players will drive technology forward more effectively if they all agree on the playbook.

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