ISSCC 2021 Preview: What to Expect

Article By : Don Scansen

ISSCC 2021 runs February 13-22. A few things will be different this year as the conference joins a long list of events going virtual...

Each year, the ISSCC technical committee prepares a selection of key technology trends in its press kit provided in the lead up to the conference. A few things will be different this year as the conference joins a long list of events going virtual. But the trends update provides a few things to consider if you are getting ready to be a 2021 ISSCC virtual attendee or just looking to extract a few high-level details on current and future directions for innovations in chip design.

It’s also worthwhile noting that the press kit that ISSCC organizers provide is excellent. It provides a fairly good explainer for those of us looking to make sense of the various figures-of-merit cited in the competitive world of IC design. Those trends can be a little difficult to grasp if you don’t work in the particular sub-field. The ISSCC media relations people deserve acknowledgment for their good work.

The technical committee breaks trends down and gathers input from the members according to five major areas shown below along with their many subcommittees.

  • Analog Systems
    • Analog Subcommittee
    • Power Management Subcommittee
    • Data Converters Subcommittee
  • Communication Systems
    • RF Subcommittee
    • Wireless Subcommittee
    • Wireline Subcommittee
  • Digital Systems
    • Digital Architectures & Systems Subcommittee
    • Digital Circuits Subcommittee
    • Machine Learning & AI Subcommittee
  • Memory
  • Innovative Topics
    • Imagers/Mems/Medical/Displays Subcommittee
    • Technology Directions Subcommittee

These are a little more obvious and straightforward than the full list of program areas for the 36 technical sessions. These seem to be arranged and titled with a mix of adherence to traditional technical fields, industry trends, and hot topics. I suppose this approach is more compelling than Memory Session I, II, III … or Digital Circuits A, B, C etc. It does make the program look much longer and more diverse than it might be to those of us just looking to boil it down to a few highlights or some related reductionist activity. Nevertheless, let us continue with the distillation.

(Distilled spirits are, after all, in high demand. Perhaps remote conferences will persist beyond the pandemic. What could be better than mixing the whiskey tasting right in with the sessions? Efficiency anyone?)

The 2021 Trends section is a nice reduction, but there are some current hot topics areas as well. Making no false claims of avoiding my own personal biases, it is better to look at such a big tech conference from a few angles:

  • System-on-chip
  • Memory
  • Automotive
  • Machine Learning / Artificial Intelligence (big data)
  • Wireless Communications
  • Wireline Communications
  • Power

Given that list then, what are some interesting trends highlighted for 2021?


This is a pet area, so it gets a mention. It’s a safe bet in any case.

Digital Architectures & Systems Subcommittee Chair Thomas Burd of AMD summed up this area:

“The major innovation efforts in mobile phones focus on three key areas: 5G, artificial intelligence (AI) and gaming. 5G cellular technology is becoming more mature and the post-5G era is gaining more focus. The 6G era will feature more antennas, more intelligence, and more use cases. The range of applications of neural network processing units (NPUs) is gradually expanding beyond image and speech recognition, to cellular performance improvement, SoC power and performance optimization. Therefore, not only the performance of the NPU is increasing, but also tiny NPUs for low-power operations are being applied everywhere. For better user experience and game quality, the main concern surrounding the display is moving from resolution to frame rate.”

Application processor trends for smartphones (source: ISSCC).

Early 2021 is seeing the completion of the transition to 5nm by all the big mobile application processor companies as Qualcomm’s Snapdragon 888 system-on-chip (SoC) hit the streets a few weeks ago while Samsung’s latest Exynos 1080 also appeared recently.

Although manufacturing continues to push ahead and chip designers are extremely sensitive to the technology platforms they deploy to, it is interesting to separate out as much as possible some of the pure design innovation at ISSCC.

Since security is getting into the conversation more, even amongst consumers, cryptographic implementations with two related circuit designs are now adopted across an array of consumer devices as well as automotive and sensor nodes. Security in many products depends upon physically unclonable functions (PUFs) and true random-number generators (TRNGs). Both security enhancing block designs are continuing to make strides in both area and power efficiency. A National University of Singapore paper will introduce an SRAM-based design that achieves an 8.7X reduction in TRNG area and a 30% improvement in PUF.

Area reductions for hardware security designs (source: ISSCC). Click on the image for a larger view.
Power consumption reductions for hardware security designs (source: ISSCC). Click on the image for a larger view.

Machine learning / artificial intelligence

Machine learning (ML) has been one of the hottest topics in recent memory, so this is one area where hype and real technology development overlap nicely. ISSCC recognized this and created a new digital subcommittee for ML and AI last year.

The focus is on datacenters, but innovation in any of power, performance, and area will be welcome in mobile processors as well as these designs continue to emphasize neural processing engines. Energy and area efficiencies continue to improve (see chart).

Trends in energy efficiency and throughput per unit area for ML inferencing processors (source: ISSCC)

The ML and AI subcommittee noted four general trends in the submissions this year:

  1. ML accelerators targeted to ultra-low-power applications are seeing growth with papers covering smart cameras, hand gesture recognition, speech recognition and keyword spotting.
  2. Compute-in-memory (CIM) architectures are gaining more prominence.
  3. Training workload support topics have seen a “marked increase.”
  4. ML processors are moving onto leading edge 5nm and 7nm technology platforms.

ML papers include the use of 3D chip stacking for the first time in the ML Processors From Cloud to Edge session. “A 1/2.3inch 12.3Mpixel with On-Chip 4.97TOPS/W CNN Processor Back-Illuminated Stacked CMOS Image Sensor” is that milestone paper. This could well be the start of a major trend in imaging considering this is a Sony paper.


Memory is always with us and always around us, but as a mature technology often gets less attention than it deserves.

In terms of maturity, there isn’t much to say about NAND flash, except that it continues to march ahead with increased capacity.

NAND flash memory capacity trends (source: ISSCC)

A major driver for the industry has become bandwidth, and those demands are definitely present for DRAM memory designers across several applications.  A couple of items to note here are a report of a 24Gbps/pin GDDR6 DRAM and the expanded bandwidth of LPDDR5 to 16Gb/channel. Hynix engineers will present “A 24Gbps/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation.”

In terms of process technology and memory, the first report of a gate all around (GAA) transistor SRAM is reported. Samsung authors will present “A 3nm Gate-All-Around SRAM: Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit” in the Advanced Embedded Memories session.

That’s a good spot for me to wrap since my interests are typically more on the process technology side. But this year’s ISSCC contains a variety of compelling content for a range of tastes. Your sipping choices might be a little more varied than the presentations, but that whiskey is optional.

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