There were three papers with impact on SoC technology: one on AI vision, one on nanosheets, one looking at power management of complex ICs...
With a nasty winter storm wreaking havoc across much of the US this week, a fully virtualized ISSCC was a less compelling reason for not leaving the house. But for remote attendees in Texas at least, they likely had to postpone their content consumption for at least a few days while dealing with more pressing issues during rolling blackouts.
The technical sessions, or the Innovation track as the ISSCC 2021 organizers refer to it, nominally scheduled for this week wrap up on Friday. (With the virtual nature of ISSCC this year, the presentations are pre-recorded and available on-demand.)
As the main paper sessions close out, there were three papers that deserve some attention for their potential impact on system-on-chip (SoC) technology.
One of the important messages to come out of ISSCC 2021 this year was a caution from Albert Theuwissen of Harvest Imaging. With the proliferation of CMOS image sensors, the potential for loss of privacy and misuse are ever-present. Theuwissen called on the ISSCC organizing committee to promote the concept of “responsible innovation.” I hope this mantra will spread.
Sony researchers presented an imaging paper that addresses the concept very nicely.
At first glance, “A 1/2.3inch 12.3Mpixel with On-Chip 4.97TOPS/W CNN Processor Back-Illuminated Stacked CMOS Image Sensor” might appear to run counter to privacy goals. The presence of convolutional neural network (CNN) computation might suggest some artificial intelligence that could be used to identify and track faces in ways that might be undesirable.
However, the Sony team is actually pushing for privacy. Ryoji Eki explained that there are three critical issues for vision artificial intelligence systems relying on cloud-based computing: latency, privacy, and power / cost.
Sony pioneered the stacking of image signal processors along with the image sensor, a technology which appears in most smartphones. In that sense, it’s no surprise that Sony continues to innovate in this area. What is a welcome surprise is that effort is made to address privacy. Stacking the CNN processor onto the CMOS image sensor will keep the AI inside the camera module. The result is that the images themselves will not be output from the chip but only the analysis results.
In other words, whoever is providing their “free” service in the cloud won’t be tempted to keep your precious photos in perpetuity.
But you might be asking, “What has this got to do with the SoC?” Granted, protecting your images and your privacy as described is a lot more about system-in-package ideas.
The idea of putting additional processing inside the camera takes the load off the cloud. It also reduces the expectations of the application processor inside the phone.
Future application processors could see some scaling back of computing blocks. Qualcomm recently launched its flagship Snapdragon 888 processor at the Snapdragon Tech Summit. Much of the fanfare of the Qualcomm technology days was built around the imaging features of the latest Snapdragon. The 888 has three image signal processors (ISPs) that provide incredible pixel throughput but consume significant silicon real estate. Although Sony’s device is only at the development stage and does not yet completely replace the ISP functionality, it is not difficult to imagine that future Sony products would add the capability, perhaps even through stacking a third (fourth anyone?) chip with the image sensor.
Although nominally an SRAM paper, “A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit” is very much a technology primer and promotion of Samsung’s upcoming gate-all-around (GAA) nanosheet transistor. The finFET replacement technology could appear in high volume products by the end of 2021.
Samsung brands their GAA transistor multi-bridge-channel MOSFET (MBCFET). The finFET is nearing the end of its useful life. The improved electrostatics of completely surrounding the transistor channel (“gate all around”) provide control of the channel on four sides compared to three in the case of the finFET.
Improved control over the channel is only part of the story. The MBCFET brings a return to the design variable that disappeared when the finFET replaced planar CMOS transistors.
The finFET set transistor width discretely. Need to improve current drive? Add another fin. Need to create a ratio of polarities between N- and P-type transistors? Add more fins to one or the other.
The MBCFET gives designers back the opportunity to continuously vary transistor width in order to better optimize power, performance, and area (PPA).
In his presentation, lead author Taejoong Song introduced SRAM design techniques for the MBCFET.
The continuously variable width of the nanosheet transistor allowed the Samsung research team to precisely balance the P / N ratio to optimize cell disturb and write margins.
To further improve SRAM performance, Samsung proposes the adaptive dual-BL (ADBL). By connecting an auxiliary bitline in parallel during the write operation, bitline resistance is lowered which, in turn, improves the write margin. Samsung reports that the ADBL will not have a negative impact on the speed or power during read operation.
Adaptive cell-power (ACP) is a second performance booster which adds header and footer transistors to the array which are activated depending on the proximity of the active cell. By activating the switch farthest from the active cell, write margin is improved.
Samsung created a 256 Mb GAA SRAM test vehicle to demonstrate the possibilities. The 56mm2 chip showed that the improved cell design of the GAA structure along with the combined ADBL plus ACP effects improved cell margin by 230 mV.
Naturally, a 3nm GAA technology will be welcome news for the next generation of SoC devices along with many other products that tend to live on the cutting edge. With the demands of on-chip memory for the SoC, the improvements to SRAM performance cited by Samsung should generate some excitement.
The final paper is even more specific to SoC design. Power and performance are the big P’s for advanced SoC design. (With wafer supply critical, though, one would never wanted to count out the A.)
Qualcomm engineers presented research targeting thread level power management for their Hexagon compute digital signal processor (CDSP).
“Thread-Level Power Management for a Current- and Temperature-Limiting System in a 7nm Hexagon Processor” was presented by Vijay Kiran Kalyanam from Qualcomm in Austin.
Qualcomm reported that previous power management techniques for SoC’s created performance issues, primarily for less power hungry operations.
By analyzing and targeting individual processor threads, the Qualcomm team demonstrated up to a 35% increase in performance for low power threads compared to global throttling techniques. The improvements were less noticeable for high power threads, but the overall average improvement across all CDSP operations was 11%.
The motivation for continuous improvement in on-chip power management for SoCs was the typically high current demands of the CDSP block and the possibility of brownouts by either the battery or system power management IC (PMIC) and resultant circuit failures.
Brownouts and downright grid failures are something the Austin-based Qualcomm team are experiencing more personally this week. With Texas hammered by extreme cold and storms, the Qualcomm design team was likely out of action for a good part of the week. For their partners at the Samsung Austin wafer fab, getting back to normal is going to take even longer as production lines were taken offline.
Thoughts go out to those in Texas and elsewhere who suffered circumstances much more extreme and difficult than production delays this week as many lacked water, heat, and power in the aftermath of the storms.