At ISSCC, TSMC said it is getting high volume throughput with its EUV system on 5nm production, with a path to 1nm...
Each successive step in semiconductor integration has taken an increasing amount of effort to achieve, but the next node — 3nm — should still arrive right on schedule, according to TSMC chairman Mark Liu. Liu made his remarks during his keynote which kicked off the (virtual) 2021 International Solid State Circuits Conference (ISSCC).
The virtual format did not affect timing of the tutorials and short course which wrapped up over the weekend.
The meat of the conference started today. Since I am in Ottawa, the conference opened at a very relaxed eastern time for me. Despite that, it was my first plenary in pyjamas. It’s also the first time I tapped away at a keyboard through a talk. I don’t know if I was just too embarrassed of my inferior typing skill or avoided it out of politeness, but I have never tried using a laptop during a live presentation.
Liu provided the first talk of the conference, Unleashing the Future of Innovation. Covering this talk in detail hits a few important points. First, TSMC is topical for a range of reasons from chip supply issues hitting industries from gaming to automobiles, strategic initiatives in the semiconductor industry and many questions about how technology scaling can continue. But when it comes down to it, semiconductor manufacturing technology is still my favorite subject.
Liu talked about the many innovations that have led us here and the many potential paths forward, in keeping with the title of this talk. But the theme that regularly popped up was the democratization of technology. As Liu noted later, technology usually starts in the hands of a few but ends up in the hands of many. TSMC sees its gigafab manufacturing as central to advanced technology getting to the largest possible number of people on the planet.
More of Moore
To push advanced technology out to the planet, you need to find ways to keep advancing technology. That was the original premise of Gordon Moore’s famous law. Transistors have to keep coming down in price. Not surprisingly, then, Liu made it clear that scaling was not slowing down. Power, performance, and density continue to improve.
Kicking off the deeper part of the innovation discussion, Liu made and then reinforced the point that 3nm was tracking with TSMC’s original schedule or slightly better than planned for introduction. We were encouraged to trust that future nodes were also meeting their early planning timelines.
Traditionally, scaling has depended upon lithography. Now with extreme ultraviolet (EUV) breakthroughs, the dimensional limits of lithography will no longer limit the industry. However, the throughput will. The important measure for EUV is the total cost of patterning. Since EUV allows many fewer masks than the multi-step patterning and multiple patterning requirements of pre-EUV technology, it is not hard to imagine it will.
Liu did note that EUV is a power hog. In terms of improvement, TSMC is getting high volume throughput at 350W illumination source power for 5nm production with a path to 1nm.
Since the advent of new gate stack materials at the core of the silicon CMOS technology earlier this century, the importance of materials innovation became obvious. TSMC introduced a high mobility channel (HMC) transistor at 5nm by incorporating germanium into the transistor fin. And materials continue to push the envelope for interconnect as well with cobalt and ruthenium.
The HMC was a material change to the fin region of the finFET, the work-horse of CMOS for many generations. But even this technology is reaching its end of life. TSMC will move to nano-sheet with gate all around (GAA) the channel to add even more electrostatic control of the transistor channel than finFET offered. Liu pointed to smaller drain induced barrier lowering and better sub-threshold swing for these new devices. But what do those metrics really offer? Well, lower power supply voltage for SRAM with TSMC’s next generation platform offering reliable cache operation at 0.46V. With ever-increasing demand for on-chip cache, getting under a half a volt will definitely improve chip power budgets.
Design technology co-optimization (DTCO) shifted thinking out of design and manufacturing silos into a cooperative regime where density increases became possible once printed feature dimensions like gate pitch could no longer define new technology nodes. DTCO has been able to keep density improvements on track with 1.8X logic gate density scaling for new nodes and 35 to 40% improvement in chip size. Getting outside the box brought improvements to important areas of system-on-chip design typically left unimproved by advancing manufacturing process technology. The DTCO improves the analog and I/O as well as the digital circuit blocks.
A Material Change
Materials Innovation will continue to drive chip technology forward. Low dimensional materials including 2D materials like hexagonal boron nitride (hBN) are getting closer to product reality. Liu highlighted an article published last year in Nature describing hBN on a wafer scale. Low-temperature processing will enable the stacking of active layers of logic and memory at the wafer level to create a true 3DIC structure.
Materials innovation maintains Moore’s vision. Without it, Liu suggests we would have no accelerator technologies (more on that was in the second plenary from Victor Peng of Xilinx) and on-chip cache would be insufficient for applications software to continue to provide improvements.
No talk about the future of semiconductor technology would be complete without a nod to chiplets. Liu noted that a lot of people were doing work on chiplets “before chiplets were cool” (or I suspect, the label had been coined). The next focus of the first talk of ISSCC 2021 was to identify 3D system fabrics as a key driver for keeping technology moving in the right direction. The main point reiterated what we have been hearing about the chiplet paradigm. It allows a domain specific technology approach. Each chiplet can be technology optimized without the tradeoffs inherent in monolithic system-on-chip design.
To look forward, the future of 3D chip stacking was highlighted. With TSMC’s SoIC (system on IC), low temperature bonding can stack a dozen dies in a vertical space less than 600¬µm thick. Liu’s slide had a 3D x-ray to which he commented, “Look at that perfect alignment.”
Tech people make the best salespeople, don’t they?
The TSMC plenary gave a nice overview of what lies ahead while maintaining calm about expectations and roadblocks. A lot more possibilities were covered, but let’s look at just one more trend.
Liu mentioned that a bandwidth deficit exists. Although data throughput is growing at 1.8X every two years, the normalized bandwidth has not quite been keeping up, advancing at only 1.6X. I/O count needs to increase to make up the difference. Fortunately, there is lots of room. Chip-to-chip interconnection density can grow four more orders of magnitude.
The Cadence continues
Liu assured the ISSCC audience that a new technology node will continue on a two-year cadence. Materials, production tool, chip design, packaging expert, along with technologists from other fields need to collaborate to get this done. In a slide summarizing the approaches that have kept Moore’s Law more or less intact, the early part of the 21st century witnessed equivalent scaling with the introduction of strained silicon and the high-k metal gate stack. FinFET structures, EUV, high-mobility channel, and DTCO pushed the industry through the next decade and a half to get to 5nm. More new transistor structures will keep us marching forward.
This quote was previously mentioned, but with the chip shortages especially at advanced nodes it’s worth hearing again. “Technology started in the hands of a few and ended up in the hands of many.” Is the most advanced technology really available to all of us? With Apple notoriously sucking up each new TSMC cutting edge node, I am not sure. Even Qualcomm and Intel see this among their biggest challenges to navigate.
Looking ahead, cutting edge wafer supply might not be the biggest headache for big chip companies. As TSMC chairman Liu sees it, a renaissance is coming. One day chip design will be as easy as writing code. That would truly be technology democratized.