Intel Gets its ‘Grove’ Back

Article By : Sally Ward-Foxton

An ebullient Pat Gelsinger laid out the strategy during Intel's Investor Day, including more than a hint of Grove-ian determination.

Intel used its Investor Day to sell Wall Street analysts on its capital spending plans over the next four years. Animated Intel CEO Pat Gelsinger bounded around the stage, invoking the name of former CEO Andrew Grove to launch a “Grove-ian execution engine” while “getting the band back together” and “renewing [Intel’s] commitment to geeks.”

Wearing a “Torrid” T-shirt, Gelsinger proclaimed that Intel is “setting a torrid pace.” In a financial context, torrid can mean “characterized by intense activity.” In the U.K., the word is more often understood to mean “very difficult”.

Based on both definitions, “torrid” is about right.

Process technologies

Pat Gelsinger at Intel Investor Day
Pat Gelsinger (Source: Intel)

Gelsinger assured investors that “Moore’s Law is alive and well,” predicting 1 trillion transistors will be packaged by 2030. “Until the periodic table is done, we are not done,” he said.

He also staged what he called a “Simba moment,” displaying a new SRAM wafer forged on Intel’s 18A process as proof the node is well on its way. The 18A node is due to arrive in 2025.

Intel is investing heavily in its foundry business, Intel Foundry Services (IFS), aiming to make it among the world’s largest by the end of the decade. Gelsinger said EU and U.S. chip legislation represented a “tail wind for Intel,” emphasizing the need for a resilient regional supply chains.

Intel is investing $20 billion in a new Ohio fab complex–just one of Intel’s 24 current construction projects. An announcement on the location of a new EU fab is “coming soon,” he added. Last week, Intel announced it is spending $5.4 billion to acquire foundry operator Tower Semiconductor, a move Gelsinger described as a “tech and talent” acquisition.

“We simply need more foundry DNA,” he said. “We also need more foundry offerings on our menu.”

Tower offers specialized processes for RF, displays and power electronics–all in short supply–while extending Intel’s global reach beyond the U.S. to Europe, Japan and Israel.

As for bleeding-edge process technology, where Intel has struggled, catching up with Taiwan Semiconductor Manufacturing Co.  and Samsung remains a challenge. Intel is still paying for mistakes made at finer nodes, effectively making it a foundry follower rather than leader. Intel’s aggressive foundry strategy includes bringing five new nodes into production over the next four years. According to Gelsinger, industry reaction has been mostly been along the lines of, “Are you crazy? Doesn’t it take two years per node?” The Intel chief countered that the rollout of all nodes is on or ahead of schedule… so far.

Enabling Intel’s accelerated timeline is close collaboration with equipment manufacturers, clearly a crucial step. The process node strategy is also based on a return to the famous Tick-Tock model of the 1990s, when then-CEO Grove pushed Intel to develop process nodes and microarchitectures in parallel, each on a two-year cadence, but in antiphase.

Intel’s comeback plan also includes reintroducing a management technique straight out of the Grove playbook called “objectives and key results.” “Why did we stop doing those?” Gelsinger mused aloud.

Intel Investor Day process node roadmap slide
Intel’s process node roadmap, updating progress on each node. (Source: Intel) (Click on image to enlarge.)

Foundry win-win

Despite Intel’s recommitment to its foundry business last year, its IDM model is viewed skeptically by some. Gelsinger confronted that skepticism directly with the phrase: “IDM makes IFS better, IFS makes IDM better.”

IFS gets the benefit of investments already made in manufacturing networks, as well as the IP blocks Intel is spending billions of dollars developing. On the flip side, the foundry push drives Intel to create more robust process design kits, better EDA tools and richer IP blocks.

IDM gives Intel control over its supply chain, “a business advantage no one else can deliver at scale,” he claimed.

Then there’s what Gelsinger calls, “The bug in the Intel business model,” something he said IFS fixes. That’s a reference to Intel’s practice of ramping a process node, boosting yields, then “when the factories are running really good, we screw it up by switching that equipment over to the next process.”

This, he continued, creates natural inefficiencies as Intel moves between nodes. With IFS, Intel claims it can run high-yield processes longer, thereby maximizing capacity usage while leveraging depreciated assets.

Intel Investor Day foundry model
Intel’s IDM 2.0 strategy fixes “the bug in the Intel business model,” CEO Gelsinger said. (Source: Intel) (Click on image to enlarge.)

Intel previously announced x86 IP licensing as part of its foundry offering. Gelsinger told investors Intel’s largest cloud customers, about one-third of its foundry pipeline, are interested in licensing its x86 designs. Going forward, Intel will be “much less religious about which architecture is used for which portion of the marketplace,” he said.

Heavy investments in foundry and manufacturing services will be required to regain chip technology leadership. That means a at least a short-term squeeze on Intel’s margins. Non-GAAP gross margins have fallen six percent on an annual basis to 52 percent in 2022, and are projected to hover between 51 and 53 percent during the 2023-2024 investment phase. By 2026, Intel’s margins will rise to as high as 58 percent. Meanwhile, operating expenses will jump between 28 and 30 percent before falling back by 2026.

“The Intel turnaround train is out of the station, and I hope you all get on board,” Gelsinger told analysts. “It is an ambitious goal, but I am confident Intel’s best days are ahead of us.”

Investors appeared unconvinced based on weak quarterly financial results: Intel shares dropping 6.7 percent after the event, a 52-week low.

This article was originally published on EE Times.

Sally Ward-Foxton covers AI technology and related issues for EETimes.com and all aspects of the European industry for EE Times Europe magazine. Sally has spent more than 15 years writing about the electronics industry from London, UK. She has written for Electronic Design, ECN, Electronic Specifier: Design, Components in Electronics, and many more. She holds a Masters’ degree in Electrical and Electronic Engineering from the University of Cambridge.

 

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