Infineon Keeps HyperRAM Relevant

Article By : Gary Hilson

With HyperRAM 3.0, Infineon is aiming the high-bandwidth, low-pin–count pSRAM-based volatile memory at applications requiring expansion RAM memory.

Nothing says enduring like a technology that’s weathered mergers and acquisitions.

Infineon Technologies’ latest iteration of its HyperRAM expansion memory can trace its roots back to Spansion, which merged with Cypress Semiconductor in late 2014. First announced in early 2015 as a companion RAM device, HyperRAM was designed for use in systems-on-chip (SoCs) and microcontrollers (MCUs), where both RAM and flash are connected to the same HyperBus interface; development of the initial HyperRAM technology was informed by the prior work on HyperBus and HyperFlash technologies.

Since the debut of HyperRAM, technologies and use cases have evolved, although the IoT has been a driving force for lower-power memory innovation over the past decade. With HyperRAM 3.0, Infineon is aiming the high-bandwidth, low-pin–count pSRAM-based volatile memory at applications requiring expansion RAM memory, including video buffering, factory automation, automotive vehicle-to-everything (V2X), and what it calls the artificial intelligence of things (AIoT), said Shivendra Singh, lead principal engineer for the company’s HyperRAM products. It’s also useful for any application that needs scratch-pad memory and data buffering for intense mathematical calculations, including embedded systems.

Infineon is positioning HyperRAM as a high-throughput, low-power expansion memory solution for high-performance embedded systems and alternative to SRAM, pSRAM, and DRAM. (Source: Infineon)

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A big selling point of HyperRAM when it was first introduced was its low pin count, which is why it’s ideal for IoT and automotive use cases and SoCs and MCUs—a smaller package saves money, allowing for cost-optimized designs because the increased per-pin data throughput of the HyperBus interface makes it possible to use MCUs with fewer pins and PCBs with fewer layers.

The small-footprint, low-pin–count interface reduces design complexity but not at the expense of performance, Singh said.

HyperRAM performs better than existing technologies in the market, such as pSRAMs and SDR DRAMs, with a far higher throughput per pin while staying efficient from power consumption perspective.

“Power consumption is another key attraction for a majority of the use cases,” he said, whether it’s saving power or enhancing the system battery life; power consumption is a concern at the edge, especially as devices become inherently smarter—the AIoT.

HyperRAM 3.0 has seen some increases in densities since the technology was first introduced with 512 Mb, now available at the high end. Support for the new extended HyperBus interface enables 800-MB/s data rates. Both are AEC-Q100–qualified and support industrial and automotive temperature grades up to 125˚C; HyperRAM 3.0 is now available in a BGA-49 package.

There was a significant gap between the first and second iterations of HyperRAM: Version 2.0 was introduced in 2021 with support for both the Octal xSPI and HyperBus JEDEC–compliant interfaces with data rates of up to 400 MB/s. The original 64Mb HyperRAM communicated at the same speed as HyperFlash, with a read throughput of up to 333 MB/s and 36-ns array read/write latency.

By combining them on the HyperBus interface, total pin count could be reduced from about 40 to 12. Although a lower pin count could mean a smaller package, the size reduction might vary depending on the use case and any desired additional functions and features.

A typical use case for HyperRAM 3.0 might for be graphics/display systems or edge AI processing in an industrial setting using a 49-ball BGA measuring 8 × 8 mm with a density of 256 Mb with 16-bit data bus width—Singh said Infineon has been able to double the data rate without increasing the clock speed.

Typical use cases for HyperRAM are graphics/display systems and edge AI processing in the industrial and consumer segments. (Source: Infineon)

HyperRAM is filling the gap between DDR4/DDR5 DRAM, which is getting increasingly complex, while DDR3 and below are in maintenance mode, he added. “DDR vendors are moving toward the higher technology node, higher performance, and higher density.”


This article was originally published on EE Times.

Gary Hilson is a general contributing editor with a focus on memory and flash technologies for EE Times.


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