Industry leaders have formed a consortium that will establish a die-to-die interconnect standard and foster an open chiplet ecosystem.
Advanced Semiconductor Engineering Inc. (ASE), AMD, Arm, Google Cloud, Intel Corp., Meta, Microsoft Corp., Qualcomm Inc., Samsung, and Taiwan Semiconductor Manufacturing Co. Ltd (TSMC) have formed an industry consortium that will establish a die-to-die interconnect standard and foster an open chiplet ecosystem.
The organization, representing a diverse ecosystem of market segments, will address customer requests for more customizable package-level integration, connecting best-in-class die-to-die interconnect and protocols from an interoperable, multi-vendor ecosystem.
The founding companies also ratified the Universal Chiplet Interconnect Express (UCIe) specification, an open industry standard developed to establish a ubiquitous interconnect at the package level. The UCIe 1.0 specification covers the die-to-die I/O physical layer, die-to-die protocols, and software stack which leverage the well-established PCI Express (PCIe) and Compute Express Link (CXL) industry standards. The specification will be available to UCIe members and available to download on the website.
The founding companies represent a wide range of industry expertise and include leading cloud service providers, foundries, system OEMs, silicon IP providers, and chip designers, and they are in the process of finalizing incorporation as an open standards body. Upon incorporation of the new UCIe industry organization later this year, member companies will begin work on the next generation of UCIe technology, including defining the chiplet form factor, management, enhanced security, and other essential protocols.
“The age of chiplets has truly arrived, driving the industry to evolve from silicon-centric thinking to system level planning and placing crucial focus on co-design of IC and package. We are confident that UCIe will play a pivotal role in enabling ecosystem efficiencies, by lowering development time and cost through open standards for interfaces between various IPs within a multi-vendor ecosystem as well as utilization of advanced package level interconnect,” said Dr. Lihong Cao, Director of Engineering and Technical Marketing at ASE. “There is broad industry recognition that Heterogeneous Integration will help bring chiplet-based designs to market. Given ASE’s expertise in packaging, assembly, and interconnect platform technology, we will provide UCIe with meaningful perspective to ensure forthcoming standards are practicable, complemented by commercially viable performance and manufacturing costs for package level manufacturing.”
“AMD is proud to continue our long history of supporting industry standards that can enable innovative solutions addressing the evolving needs of our customers. We have been a leader in chiplet technology and welcome a multi-vendor chiplet ecosystem to enable customizable third-party integration. The UCIe standard will be a key factor to drive systems innovation leveraging heterogeneous compute engines and accelerators that will enable the best solutions optimized for performance, cost, and power efficiency,” said Mark Papermaster, Executive Vice President and Chief Technology Officer, AMD.
“Interoperability is essential to removing fragmentation across the Arm ecosystem, and across the industry. By collaborating with other leaders in computing, Arm is committed to helping develop standards and specifications like UCIe to enable the system designs of our future,” said Andy Rose, chief system architect and fellow, Arm.
“An open, standards based chiplet ecosystem is an important enabler to foster Systems on Chip (SoC) designs as the integration point for an optimized system. Google Cloud is pleased to contribute to the Universal Chiplet Interconnect Express standard in service of the development of a multi-vendor inter-operable chiplet marketplace for the benefit of the industry,” commented Partha Ranganathan, Google Fellow and Vice President.
Sandra Rivera, Executive Vice President, Intel, and GM, Data Center & AI, said integrating multiple chiplets in a package to deliver product innovation across market segments is the future of the semiconductor industry and a pillar of Intel’s IDM 2.0 strategy. “Critical to this future is an open chiplet ecosystem with key industry partners working together under the UCIe Consortium toward a common goal of transforming the way the industry delivers new products and continues to deliver on the promise of Moore’s Law,” she noted.
“Meta is excited to join UCIe as a founding member to enable and foster a standards-based die-to-die interconnect. Meta initiated ecosystem development to promote chiplet-based SOCs via the Open Compute Project (OCP) and is pleased to collaborate with other industry leaders via UCIe consortium for the ongoing and future success in this area,” said Vijay Rao, Directory of Technology and Strategy, Meta.
“Microsoft is joining the UCIe industry organization to accelerate the pace of datacenter innovation and enable new breakthroughs in silicon design. We look forward to combining efforts of the organization with our own achievements to drive step-function improvements in silicon architecture for the benefit of our customers,” said Dr. Leendert van Doorn, Distinguished Engineer, Azure, Microsoft.
Dr. Edward Tiedemann, Senior Vice-President of Engineering at Qualcomm Technologies, noted that the UCIe should move chiplet technology forward, an important technology to address the challenges in the increasingly complex semiconductor systems.
“Samsung envisions chiplet technology becoming necessary for performance gains in computing systems as process nodes continue to scale, with dies inside each package eventually communicating through a single language. We expect the UCIe Consortium to foster a vibrant chiplet ecosystem and establish the framework for a viable open-standard interface industry-wide. As a total solutions provider for memory, logic, and foundry, Samsung anticipates spearheading consortium efforts to further identify the best ways for enhancing system performance through chiplet technology,” said Cheolmin Park, Vice President of Memory Product Planning Team at Samsung Electronics.
“TSMC is pleased to participate in this industry-wide consortium that will broaden the ecosystem for package-level integration. TSMC offers various silicon and packaging technologies that provide multiple implementation options for heterogeneous UCIe devices,” said Lee-Chung Lu, TSMC Fellow and Vice President of Design and Technology Platform.