Imec proposes 2D materials for FET scaling

Article By : Imec

An Imec collaboration demonstrated that 2D materials with anisotropicity and a smaller effective mass could help in extending Moore’s law into the sub-5nm gate length.

Imec researchers, together with scientists from KU Leuven in Belgium and Pisa University in Italy, have performed the first material-device-circuit level co-optimisation of FETs based on 2D materials for high-performance logic applications scaled beyond the 10nm technology node. Imec has also presented designs that would allow using monolayer 2D materials to enable Moore’s Law below 5nm gate length.

The 2D promise

2D materials may be used to create the ultimate transistor with a channel thickness down to the level of single atoms and gate length of few nanometres. A key driver that allowed the industry to follow Moore’s Law and continue producing powerful chips was the continued scaling of the gate length. To counter the resulting negative short-channel effects, chip manufacturers have moved from planar transistors to FinFETs. They are now introducing other transistor architectures, such as nanowire FETs.

Imec is looking further at replacing the transistor channel material with 2D materials as some of the prime candidates.

To fit FETs based on 2D materials into the scaling roadmap, it is essential to understand how their characteristics relate to their behaviour in digital circuits. In a paper published in Scientific Reports, Imec scientists and their collaborators have presented guidelines on how to choose materials, design the devices and optimise performance to arrive at circuits that meet the requirements for sub-10nm high-performance logic chips.

Their findings demonstrate the need to use 2D materials with anisotropicity and a smaller effective mass in the transport direction. Using one such material, monolayer black-phosphorus, the researchers have presented new device designs. These designs reveal that for sub-5nm gate lengths, 2D electrostatics arising from gate stack design become more of a challenge than direct source-to-drain tunnelling. Note that, in the case of 3D semiconductors such as Si, scaling gate length so aggressively is practically impossible.

These results were published in Scientific Reports: T. Agarwal, G. Fiori, B. Soree, I. Radu, P. Raghavan, G. Iannaccone, W. Dehaene, M. Heyns – Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes (SREP-16-50433).

Subscribe to Newsletter

Leave a comment