IC Design: Going Back to 2-D?

Article By : Don Scansen

ICs, once planar, had to go 3-D to keep progressing. Future progress will probably take ICs back to 2-D, however.

We used to think of planar transistors in the glory days of classical Dennard scaling in two-dimensional terms. Material specifications were simplified into things like sheet resistance in ohms per square. The abstraction of the devices was was all 2-D, and most of the assumptions and the device modeling for understanding MOSFET operation for circuit design were simplified as much as possible to a pair of axes.

We might have thought of planar MOSFETs as 2-D transistors, at least until the assumptions broke down and the complexity of the device physics took off.

Eventually, planar CMOS turned to the third dimension with Intel’s TriGate and other flavors of the finFET. We called these 3-D transistors.

The original 3D finFET from Intel (source: Intel)

But as we frequently see in technology (ad nauseam perhaps in this column?), terms need to be readjusted, adapted, or re-used. We continue to use MOSFET despite the replacement of the oxide of silicon’s “O” with high-K insulators. MISFET is more accurate. It’s easier to say too. And it’s got the ring of a term sometimes used to describe more than a few of us in the technology field.

A recent Nature online journal article provided insights into the future of semiconductor technology and attracted the attention of the editors here at EETimes. Promises and prospects of two-dimensional transistors discussed the end of the line for the silicon material system. It isn’t just that finFETs are running out of steam. (They surely are as some sort of gate all around — GAA — will be required beyond 3nm.)

Future devices will be thin enough (a monolayer or two) to be considered two-dimensional. And it might go without saying, but traditional 3-D semiconductors like silicon don’t work well in that regime.

Enter the class of materials known as transition metal dichalcogenides (TMD or TMCD). To name a few, these include molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), molybdenum ditelluride (MoTe2), tungsten diselenide (WSe2), and tungsten disulfide (WS2).

The lead author of the Nature article, Xiangfeng Duan, is from the California Nanosystems Institute at UCLA along with one other author. Other representation includes Hunan University (China) and the Samsung Advanced Institute of Technology (SAIT, Korea). These collaborators addressed the potential of the TMD materials for 2-D transistors in future IC production.


The Nature article is current, but first let’s take a look at a couple of other sources for prognostication.

IMEC WS2 channel transistor (source: IEEE)

When it comes to a long view into future technology, one of the best sources is IMEC. At the last International Electron Devices Meeting (IEDM) held in December, a plenary talk by Sri Samevadam looked at the future of scaling from several angles from materials to “deconstructed chips” (possibly avoiding the term chiplet).

For future scaling of standard cell logic — to get below a 4 track cell — IMEC looks to transistors based on 2D materials. Their roadmap slots the 2D transistor at “1nm” technology and beyond. This is after the nanosheet era as well as the stacked nanosheets of complimentary polarity, CFET, proposed around “1.5nm” for four track cells. That represents a lot of technology turnover in a fairly short time, only a decade or so.

It is safe to assume that IMEC is looking to WSi2 for the channel material. It could well be the most promising as an IMEC team reported the first fabrication of these 2D MISFETs on a production line on 300mm wafers. The IEEE link is here, but it requires a subscription.

Since the Nature article makes comparisons to 2021 as quoted in the last of the old International Technology Roadmap for Semiconductors (ITRS) that was released in 2015. That edition forecast out to 2021 with a silicon CMOS transistor maximum on current target of just shy of 1,500 µA/mm. Let’s compare that to the more recent official roadmap.

From bulk MOSFET to 2D MISFET (source: Nature)

The ITRS was replaced by the Ineternational Roadmap for Devices and Systems (IRDS, and it’s trademarked now) which endeavors to look at the advancement of microlectronics more holistically. The old ITRS team seemed to keep the industry on the rails for a long time, but that doesn’t mean it couldn’t be adapted to address new industry challenges.

And the latest IRDS release is reasonably timely with its 2020 date. It is free to IEEE members.

Since a lot of the old band is back together for the IRDS, the format is familiar, but there has been a bit of rejuggling of the old working groups. For our purposes, we will be most interested in the More Moore (MM) and the Beyond CMOS (BC) roadmaps.

Checking the latest MM to verify predictions, the maximum on-current for conventional CMOS should be just a little over 1,700 µA/µm. Using the old ITRS roadmap makes the new material drive current numbers a little more palatable, so there was some sandbagging of silicon there. For the purposes of comparing a new class of 2D materials to conventional technology, the range is close enough.

So far, so good, but let’s check what IRDS BC technologists think. We don’t want to find ourselves in flat earth territory.

The folks looking beyond the grave of current technology suggest that we will see a transition to 2D materials in 2028 which is the timeline for the “1.5nm” node range.

Current density does not lie

The more inquisitive will read the full paper and be rewarded with more than just seeing that the sub-heading was ripped straight out of it.

The authors of the 2D transistor review propose that many of the metrics used to determine the suitability or gauge the progress of the new materials may be holding them back. Ultimately, performance matters — not breaking laboratory world records for specific physical properties.

For continued real world scaling, the issues are power, performance, area and cost (P-P-A-C). New transistor designs and materials will only make it into volume production if they fit into this engineering balance.

For a transistor, the performance metric is current drive capability. We touched on this earlier, calling it on current. You may also recognize saturation drive current, and it is measured per unit of device width. Many readers will know this well (but may have already tuned out). The benchmark measurements are ION in µA/µm.

Duan and collaborators suggest that other common metrics like mobility (µ) and contact resistance (RC) may not tell the whole story. Taking it another step, these two data points may lead to “ambiguous and sometimes contradicting claims.” The researchers point out reports where high mobility or low contact resistance did not translate into high drive current.

What’s the point?

The Nature paper argues that it makes little sense to concentrate on improving mobility or contact resistance. That tends to leave researchers getting lost in the device modeling just to explain the current density achieved by those transistors. Duan (et al) would like the 2D transistors to be compared to conventional technology on the one indicator that will translate into a future generation of high performance products. Right now, though, the best numbers are around half (or less depending on the particular TMD material) of conventional silicon transistors.

The Promise, the Challenges

The issue with scaling of the silicon channel is that mobility falls off rapidly with reduced thickness which is anticipated beyond current 5nm technology (body thickness below 3nm). The TMD 2D materials start to enjoy a competitive advantage over silicon in this range, happily maintaining mobility below 1nm thickness.

Oddly, we are looking at mobility again. Strange?

Let’s consider silicon. This semiconductor is well characterized, to put it mildly. The mechanisms are well known, and both the decline in mobility in thin layers and the reasons behind it are accepted.

The body of knowledge for the 2D materials fractional, at best. However, the consistent mobility values as layers approach atomic thickness support the general understanding. This is a strong indicator for developing the 2D materials for production with a physical explanation for their advantages at future technology nodes.

But questions certainly remain as the clock ticks down on the 2028 introduction date proposed in the IRDS roadmap.

Getting the most out of 2D transistors (best saturation drive current) depends on four main factors: intrinsic material properties, contact resistance, the semiconductor-dielectric interface, and heat dissipation.

Let’s think about a couple of those.

Transistors in current technologies depend upon heavily doped source and drain regions to minimize the contact resistance. A 2-D crystal lattice will not support this technique since it is atomically thin. New devices demand a new approach.

Several new contact technologies have been proposed. Edge contacts have been demonstrated. These include lateral metal-semiconductor heterostructures — promising, interesting, and unproven.

Another interesting new technique has shown the most promise, according to Duan and colleagues. A direct van der Walls (vdW) contact may provide a clean interface and tunable metal-semiconductor barrier. Read more about these vdW contacts in another online publication of the Nature Journal, 2D Materials and Applications.

Devices designed around a layer one to a few atoms thick will obviously rely on a suitable subtrate material as the foundation. Thermal performance is a major consideration, and boron nitride (BN) has shown great promise. It offers another advantage in terms of the quality of interface which in turn will help with the integration of high-K gate dielectrics for the 2-D transistor.

Four key components of the idealized 2D MISFET (source: Nature)

Although great strides have been made within the key areas, it is important to reiterate the comment that “despite some pioneering efforts in these important aspects, simultaneous optimization of channel material, contact, dielectric, thermal interface and device geometry has not been achieved.”

There is much to do and not much time. The ultimate winner for the “1.5nm” generation will only be revealed once and for all when Samsung or TSMC makes an announcement. Take note: The Samsung Advanced Institute of Technology is a contributor to this work.

Next, Duan and his co-authors examined the “lab-to-fab transition.”

Although boron nitride has shown great promise for production scale 300mm substrates, most attempts to deposit TMDs at that scale yield polycrystalline rather than the desired monocrystalline material.

Many 2D materials suffer poor adhesion with adjacent layers in the stack leaving structures prone to chemical ingress during processing leading to layer peeling and device failure during or after manufacture.

Let’s leave it at the major stumbling blocks. These are significant enough. There’s no need to spread pessimism.

What will it take?

We just touched on the idea that TSMC or Samsung will be the adopters of most importance for any new material or device architecture for future technology. We may not yet know what their plans are, but their excellence in process integration may offer the answer to 2D transistor uptake.

The Nature contributors recognize that the 2-D transistor will need a “killer application” to make it to production. It’s the old story of the established player and the enormous capital investment in silicon wafer production. The authors admit, “it is unlikely that 2D semiconductors would fully replace silicon in the foreseeable future.” I am not sure about the definition of “foreseeable.” 2028 will be here in a heartbeat.

Instead, they argue that if you can’t beat ’em, join ’em.

The answer may lie in 3D integration. Rather than the 3D system integration that is often discussed for the More than Moore solution to scaling, this would be the creation of true, monolithic 3D integrated circuits.

The “intrinsic free-standing and dangling-bond-free nature of 2D crystals makes them well suited for multi-tier integration.” One of the main issues with adoption of the 2D devices was the substrate. Stacking them over conventional silicon front ends may reduce one challenge.

The 2D materials can be produced at lower temperatures than silicon front ends and are compatible with current back end of line (BEOL) metallization. Beyond the ability to offer stacking of active circuitry layers on the same wafer substrate, integration into the BEOL opens up another opportunity. Back gating of the 2D channel is built right into this flow as IMEC demonstrated with their WSi2 transistors.

IMEC back gated WS2 2D transistor integrated into a standard metallization process (source: IEEE)

Flexible electronics presents another potential road to 2-D adoption. Flexible devices are typically based on organic semiconductors which suffer orders of magnitude lower performance. 2-D materials are high performance and inherently flexible which could open up a range of new possibilities for high speed circuits that are “flexible, foldable or conformal to irregular surfaces.”

Despite the challenges, Duan and his co-authors are confident that there are no fundamental roadblocks preventing the adoption of 2-D materials for integrated circuit transistors at an industrial scale.

The transition to 2-D transistors seems inevitable. Just a few years ago, such a radical change would have been unthinkable. A quick tour through the technology roadmaps and predictions show a lot of rapid turnover of major changes for integrated circuit technology in the coming years. In that context, a mouthful of materials like molybdenum ditelluride does not seem so strange.

Of course, there is always the next big thing beyond the horizon. What’s next? If we are dropping D’s, 2-D will shrink to 1-D. Technology oracles predict 1-D carbon nanotube transistors.

Let’s just say change is going to be our constant companion in semiconductor technology.

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