GUC Unveils Die-on-Die Interface IP Using TSMC N5 and N6 Process

Article By : Global Unichip Corp.

GUC has announced GLink-3D die-on-die interface IP using TSMC’s N5 and N6 processes, and 3DFabric packaging technology for AI, HPC, and networking applications.

Global Unichip Corp. (GUC) has announced GLink-3D die-on-die interface IP using TSMC’s N5 and N6 processes, and 3DFabric advanced packaging technology for AI, high-performance computing (HPC), and networking applications.

The rapid growth in memory demand from the AI, HPC, and networking sectors is driving the increase in SRAM to logic ratio. Logic gains higher density and performance when scaled to N5/N3 process nodes; but SRAM scaling from N7 to N5/N3 is moderate. SRAM/logic disintegration allows the implementation of separate SRAM and logic at the most efficient process nodes.

Layers of CPU and SRAM (last level cache, packet buffers) dies can be assembled over and under interconnect/IO dies using TSMC 3DFabric packaging technology. Such expandable SRAM and modular computing applications are enabled by GUC’s GLink-3D high bandwidth, low latency, low power, and point-to-multipoint interface between 3D stacked dies. CPUs, SRAMs, interconnects, and I/Os (SerDes, HBM, DDR) can be implemented in the most efficient process nodes. Different die combinations can be assembled to address different market segments. At boot time, assembled SRAM and CPU dies are identified, unique die IDs are distributed, available memory space and computing resources are defined, and a point-to-multipoint GLink-3D interface to the stacked dies is enabled.

TSMC’s 3DFabric SoIC platform technology allows much more efficient connectivity. GLink-3D achieved six times higher bandwidth/area density, six times lower latency and 2X lower power consumption than best-in-class 2.5D interface GLink-2.0 (it was taped out in December 2020). Several 3D die stacks can be assembled using CoWoS and InFO_oS, interconnected using GLink-2.5D links and combined with HBM memories.

“GLink-3D is a new addition to a rich portfolio of best-in-class and silicon-proven HBM2E/3 PHY/Controller and GLink-2.5D IPs. CoWoS, InFO_oS, 3DIC expertise, package design, electrical and thermal simulations, DFT and production testing under one GUC roof provide our ASIC customers with quick design cycles, fast bring up  and production ramp up,” explained Dr. Ken Chen, president of GUC.

Igor Elkanovich, CTO of GUC, said, “3D die stacking technology will start a revolution in the way we design HPC, AI and network processors. Die-to-die interface is not limited any more to the die boundary, it can be located exactly where processors need to connect to SRAM and additional CPUs. 3DFabric and GLink-3D pave way to the processors of the future, combining huge and scalable processing power with vast, high bandwidth and low latency memory, when every component is implemented using the most efficient process node.”

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