FPGA Development Opens Up

Article By : Steve Leibson

The Open Source FPGA Foundation sets ambitious goals for 2022, including design training and prototype devices.

An open approach to FPGA development is emerging as promoters seek to foster an open-source ecosystem of development tools that will extend the technology.

Pierre-Emmanuel Gaillardon of the Open Source FPGA Foundation noted during an event co-located with this year’s Design Automation Conference that multiple projects are already underway. Key challenges include open development of core FPGA fabrics, along with accessible tooling and design flows.

Aspiring entrants to the FPGA market will be shut out without these advances, Gaillardon asserted.

Pierre-Emmanuel Gaillardon, co-chair of the Open Source FPGA Foundation.

Available open-source tools include logic synthesis, floor planning, place-and-route, static timing analysis and JTAG-based debugging tools. Still needed is a tailored FPGA design interface. Gaillardon said the list of FPGA development tools remains long and largely unaddressed, including a TcL interpreter and compiler wrapper.

He described four organizational goals to be achieved by the foundation in the coming year:

  • Train 10,000 students in FPGA design and the use of design tools
  • Tape out more than 25 open-source FPGA chips in more than 20 countries
  • Develop a general-purpose GUI
  • Create a commercial-grade, open-source FPGA tool flow

Training more designers is essential for a vibrant FPGA ecosystem, Gaillardon added. FPGA vendors have faced the same problem for decades: Only a handful of engineers understand FPGA design – on the order of perhaps tens of thousands – while there are literally millions of software developers.

Seeking to address that disparity, it’s likely that current commercial FPGA vendors such as Achronix, Efinix, Gowin, Intel, Lattice, Microchip, QuickLogic and Xilinx would support the training goal. (Representatives from QuickLogic and Xilinx also spoke at the FPGA event.)

Still, it unlikely commercial vendors would be willing to release details of their proprietary FPGA configuration bitstreams to dovetail with the foundation’s open-source tools, with some exceptions. There are a variety of reasons for secrecy:

  • It’s possible to destroy a new FPGA with an errant bitstream, hence vendors seek to control bitstream generation to prevent the destruction of customers’ expensive silicon.
  • Bitstreams are often secured through encryption and authentication. Publicly documenting a bitstream format can aid unauthorized bitstream decryption.
  • Thoroughly documenting and commercializing a bitstream for each FPGA would require significant effort, and is unlikely to generate enough incremental revenue to recoup the investment.
  • Finally, FPGAs ceased two decades ago to be simple collections of logic blocks. The current Xilinx Versal device family, for example, includes microprocessor cores, AI accelerators and a network-on-chip, along with on-chip, programmable logic resources. All are configured by the bitstream, and extend beyond the capabilities of open-source FPGA development tools. Hence, new designs would not benefit from the open-source foundation’s efforts.

Thus, the goal of taping out more than 25 new open-source FPGA chips over the next year seems the logical path. New tools need to operate on a documented, open FPGA fabric, and there is much progress in this area.

Jeff DiCorpo, senior vice president for business development at efabless.com, said its partnership with SkyWater Technology includes chip development services such as design automation and flow, die fabrication and testing through a wafer shuttle service, device packaging along with assembled evaluation boards with packaged devices.

The SkyWater, Bloomington, Minn., provides efabless.com with access to its 130-nm, CMOS process technology. The established process node delivers a low-cost path for creating proof-of-concept ICs for student projects. Several FPGA projects created with open tools have already been fabricated via the partnership.

Three FPGA project chips developed via efabless.com’s wafer shuttle service. (Source: efabless.com)

During a panel discussion, Brian Faith, QuickLogic’s president and CEO, described his conversion to the open FPGA philosophy after attending an earlier FPGA conference in France. He arrived as a skeptic and returned a believer, Faith said. Among the reasons are more than adequate open-source tools for FPGA development. Those tools enable rapid technological innovation by an expanded group of eager engineers.

As a result, Faith added, QuickLogic has contributed data to allow open-source tools to generate bitstreams for its FPGAs. He also acknowledged that QuickLogic’s focus on small and mid-sized FPGAs colors his thinking.

Ramine Roane, vice president of AI and software at Xilinx, offered a different perspective: The best way for open-source tools to intersect the FPGA market is at the application level. For example, Roane said open FPGA tools and IP were the best way to involve AI and machine learning software developers. FPGAs could serve as accelerators, meaning developers “don’t even see the FPGA,” Roane said.

This article was originally published on EE Times.

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