The SOC2 was designed and taped out in a TSMC 16nm technology by Bar-Ilan University SoC Lab, as part of the HiPer Consortium.
Flex Logix Technologies Inc. and CEVA Inc. have unveiled the world’s first successful silicon implementation using Flex Logix’s EFLX embedded FPGA (eFPGA) connected to a CEVA-X2 DSP instruction extension interface. Enabling flexible and changeable instruction sets to meet demanding and changing processing workloads, the ASIC, known as SOC2, was designed and taped out in a TSMC 16nm technology by Bar-Ilan University SoC Lab, as part of the HiPer Consortium, backed by the Israeli Innovation Authority (IIA).
“The ability to add custom instructions to minimize power and maximize performance efficiency of embedded processors has been around for decades,” said Andy Jaros, VP of Sales and Marketing for Flex Logix’s eFPGA IP. “The ISA extension capability works great for targeted applications, but it can be a costly solution when the application changes or new use cases need different instructions requiring a new chip to be developed. By working with CEVA and the HiPer Consortium, the SOC2 proves that reconfigurable computing is here with a DSP Instruction Set Architecture (ISA) that can be adapted to different workloads with custom hard-wired instructions that can be changed at any time in the future.”
“Being part of the HiPer Consortium, we were excited to work with Bar-Ilan University SoC Lab team and Flex Logix to test out new capabilities for the CEVA-X2 DSP that had never been tried before,” said Erez Bar-Niv, CEVA’s Chief Technology Officer. “The SOC2 contains two processing clusters, each containing two CEVA-X2 DSP cores and EFLX eFPGA for programming and executing DSP instructions extensions, connected using the CEVA-Xtend mechanism. Flex Logix and CEVA’s mutual customers can now confidently utilize custom instructions to extract more value from their ASIC by being able to target different DSP applications on top of communication and sound with a customizable ISA post manufacturing.”
EFLX eFPGA can be used anywhere in an ASIC architecture. In addition to the ISA extension interface, EFLX has been used for packet processing, security, encryption, IO muxes, and general purpose algorithm acceleration. Using EFLX, chip developers can implement eFPGA from a few thousand LUTs to over a million LUTs with performance and density per square millimeter similar to leading FPGA companies in the same process generation. EFLX eFPGA is modular so arrays can be spread throughout the chip, can have all-logic or be heavy-DSP, and can integrate RAM. EFLX eFPGA is available today in popular 12, 16, 22, 28 and 40nm process nodes and in development at 7nm with more advanced nodes planned for future release.
The CEVA-X2 is a multipurpose hybrid DSP and Controller based on a five-way VLIW/SIMD architecture with a 10-stage pipeline, operating at over 1GHz at a 16nm process. As an advanced DSP optimized for intensive workloads, it has been specifically designed to tackle use-cases such as 5G PHY control, multi-microphone beamforming, AI processing and neural network implementations. CEVA-X2 supports various software needs using the extensive CEVA DSP Library, CEVA Neural Network Library, and a vast ecosystem partner offerings of software solutions for any application.