We will see a clear scaling trend delay in Logic 3nm? TechInsights has updated the scaling trend for our customers from the 2021 Process and Design Annual Seminar. Yuzo Fukuzaki In summary, NAND2 cell scaling trend has seen boosted gate pitch scaling, while SRAM scaling trend is flat NAND2 cell scaling trend by year […]
You can find more details in ICMTS 2022 tutorial presentation by Yuzo Fukuzaki.
TechInsights has added the most recent data from our Digital Floorplan Analysis and TechInsights’ speculation for TSMC N3 technology that we expect to see in the next 18 months. We have used an arbitrary unit in the information below, however for details, you can contact TechInsights.
Note that N3 (TechInsights’ speculative process technology, having lowest CPP ; Contacted Poly Pitch) will fall on the DTCO scaling trend shown in the chart at bottom right. Also seen is the NAND2 cell area scaling delay in 2023 (bottom left chart). From this, it also confirms that HD SRAM cell area scaling has been delayed from 2018 (top left chart) due to a lack of DTCO options to implement scaling of these cells (compared with the 2 charts on the right). Further, 3nm process node release date has been delayed, further impacting and delaying the scaling trends that we have historically seen maintained by the industry.
If TSMC N3 parts were available in 1H22 as originally planned, the trend would have been maintained (shown by the broken line). TSMC N3 will see manufacturing ramp-up beginning in 2H22, and we expect parts to be available to us 1H23. The root cause of this delay is simply due to technology release delays from the initial plan.
TSMC on track to move 3nm process to volume production in 2H22 (Digitimes)
TSMC, ‘3-nano’ confidence… Focus on Samsung’s ‘Foundry’ strategy (Korean) (Newdaily)