Andes Adds 1,024-Bit Vectors Andes has a new high-end CPU that handles the longest vectors yet for RISC-V as well as a new small entry-level CPU for small connected systems. Bryon Moyer New Andes CPU cores expand the high and low ends of the company’s RISC-V offering. Announced for the RISC-V Summit, the AX45MPV adds […]
New Andes CPU cores expand the high and low ends of the company’s RISC-V offering. Announced for the RISC-V Summit, the AX45MPV adds a vector unit to the existing AX45MP; the D23 adds a pipeline cycle, a DSP, and an FPU to the base N22 configuration.
Andes has implemented vector units (sometimes called vector processing units, or VPUs) before; this launch adds them to an application-class design capable of up to eight-core clusters. The AX45MPV has an MMU that allows it to host Linux for applications such as cryptography, image processing, and machine learning. A maximum hardware vector length of 1,024 bits doubles that of the company’s previous VPUs, in turn doubling throughput per cycle.
For scalar operations, the AX45MPV achieves 3.27 Dmips per megahertz and 5.63 CoreMarks per megahertz. Physical-memory protection (PMP) and programmable physical-memory attributes increase core security. The CPU is available now for evaluation.
Meanwhile, the tiny new Andes D23 handles sensor fusion, motor control, and other functions for IoT and wearable systems. In addition to the extra blocks and pipeline stage, it adds new instructions and a supervisor mode. Cache ECC boosts reliability compared with the original N22. Performance benchmarks are 2.0 Dmips per megahertz and 4.13 CoreMarks per megahertz. It’s scheduled to be available for select-customer evaluation in 1Q23, with broad evaluation scheduled for 3 Q23.