NXP Chip Combines Car Functions

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NXP Chip Combines Car Functions NXP’s S32Z2 and S32E2 processors integrate multiple low-level automotive functions into a single SoC that preserves isolation between virtualized electronic control units (ECUs) from software through I/Os. Bryon Moyer At a time when most automotive processors address AI and autonomy, NXP has launched two new automotive SoCs that integrate the […]

NXP Chip Combines Car Functions

NXP’s S32Z2 and S32E2 processors integrate multiple low-level automotive functions into a single SoC that preserves isolation between virtualized electronic control units (ECUs) from software through I/Os.

Bryon Moyer
Bryon Moyer

At a time when most automotive processors address AI and autonomy, NXP has launched two new automotive SoCs that integrate the nitty-gritty work of driving: the real-time requirements of low-level sensors, batteries, actuators, and motors, implemented today by multiple single-purpose electronic control units (ECUs). With eight Cortex-R52 real-time cores and several additional CPUs, the S32Z2 (Z2) and S32E2 (E2) series integrate the functions of several low-level ECUs on a single chip.

Manufactured in 16nm silicon and clocked at up to 1.0GHz, the two devices address both those customers who want to perform only real-time control computing (Z2), with other chips controlling mechanical units such as brakes or the propulsion system, and those who wish to go further to actuate those systems directly from the chip (E2). What were individual ECUs come together as virtual ECUs in an architecture that preserves isolation between virtual ECUs all the way from the processing cores to the I/Os for safe, reliable operation. Dual-core lockstep configurations are options for the real-time cores and enforced for others, making the chips suitable for ASIL-B or ASIL-D systems. Thermal design power (TDP) is in the 3-5W range.

Accompanying the Cortex-R52 cores are DSPs for general use and for executing limited AI models as well as other Cortex-M cores in blocks that offload critical functions from the real-time processors. They include security, an Ethernet switch, and an offload engine for managing a variety of other automotive communication protocols, most prominent among them CANbus.

Level-1 cache and tightly coupled memories (TCM) for each core accompany 19MB of additional SRAM and up to 64MB of integrated code flash. Memory expansion through an LDDR4 port allows for execute-in-place (XIP). A wide variety of I/Os provide flexibility for designers working out how to build electrified software-defined vehicles. Samples are available now; production units are scheduled for 4Q23.

NXP’s view of high- and low-level driving control

NXP S32Z2 architecture

NXP S32E1 architecture

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