Chiplets a new design methodology?

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Chiplets a new design methodology? G. Dan Hutcheson The Chip Insider® Are Chiplets a new design methodology? There’s been a great marketing war over nomenclature ownership ever since the industry recognized the future after monolithic SoCs is polylithic SiPs (i.e. single-die System-on-Chip versus multi-die System-in-Package). The technological approach is ancient. In the beginning, Jack Kilby’s […]

Chiplets a new design methodology?

G. Dan Hutcheson
G. Dan Hutcheson

The Chip Insider®

Are Chiplets a new design methodology? There’s been a great marketing war over nomenclature ownership ever since the industry recognized the future after monolithic SoCs is polylithic SiPs (i.e. single-die System-on-Chip versus multi-die System-in-Package). The technological approach is ancient. In the beginning, Jack Kilby’s Integrated Circuit, circa 1958, was made up of multiple die wire-bonded together on a single substrate… I expect the new UCIe initiative (Universal Chiplet Interconnect express) to lock in the use of chiplet… The other ‘too many toos’ problems are being resolved as well… Companies are figuring out how to test and deliver KGD which are … Intel was the first to announce this … The too difficult to design barrier is … There are also new opportunities here for EDA suppliers to make a polylithic design appear… There are new opportunities in areas such… The point is, it doesn’t matter what you call it, the opportunity is there.

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