Extreme ultraviolet lithography still faces reliability issues, but it's ready for volume use, Intel's EUV chief said
Extreme ultraviolet (EUV) lithography is “ready for introduction…and running in volume for technology development,” said the head of Intel’s EUV program. But engineers still face several challenges harnessing the complex and costly systems to make leading-edge chips in high volume, she said.
Britt Turkot, a fellow and director of EUV at Intel, said the room-sized systems are running in its giant Portland, Oregon fab. She would not say how or if EUV will be used for the company’s 10nm products ramping now or its planned 7nm node.
Intel was among the semiconductor companies that helped pioneer the technology more than two decades ago, but is among the last to confirm its use. Last year, rival Samsung and TSMC separately announced they were ramping 7nm nodes using EUV systems to print their finest features.
However, in an indication of the challenges still ahead, two sources said TSMC’s N7+ is using EUV for only four metal layers. That means it still requires use of double patterning with traditional immersion steppers for some metal layers.
TSMC’s decision probably is “about throughput, how many EUV machines they have and cost trade-offs…Samsung may have invested more in EUV machines,” said one source who asked not to be named.
The systems cost about $150 million each, and several are needed for a commercial production line.
“We indeed deploy double patterning in many layers. The decision to use immersion double patterning vs. EUV is based on a number of considerations. EUV’s cost, [and] maturity versus immersion definitely is important,” said a TSMC spokeswoman who declined to comment on how many metal layers the foundry uses EUV for its N7+ node.
Separately, one source said Samsung is aggressively undercutting prices for its 7nm node with EUV, offering some startups a full mask set for less than a multi-layer mask (MLM) set at its rival. TSMC introduced the MLM mask sets in 2007 to lower costs for small-volume runs. They are said to be about 60% of the cost of a full mask set.
Samsung declined to comment on its foundry pricing or how it uses of EUV. One Samsung executive speculated that Intel was late with its 10nm process in part because its ambitious use of contact over active gate (COAG) structures. Samsung will gradually move toward COAG, he said, declining to give details.
In a recent blog, Intel’s chief engineering officer, Murthy Renduchintala characterized the company’s 10nm node as in some ways ambitious. But he said chips using it are now in production and work on a 7nm node is making good progress.
In an interview with EE Times, Turkot said Intel has not yet decided on how many metal layers it will use with EUV. Choosing which layers to apply EUV is as much art as science, she suggested.
“Cost per layer is not a straightforward calculation — it’s not straight economics,” she said.
For example, a single EUV exposure can sometimes reduce the mask count for a layer by a ratio of up to 5:1. However, double patterning with immersion steppers can help reduce edge-placement errors, she noted.
Turkot explains the complexity behind EUV reliability
System reliability is another variable impacting cost. Intel currently reports system uptime of about 75-80% for its EUV systems. “The number is not where it needs to be long term, but its good enough for introduction — we want it to be like immersion today, in the '90s,” Turkot said.
The good news is downtime is “more predictable. It was extremely unpredictable in the past, and [that made it] difficult to sustain a product line and run a volume line for development,” she said.
Most of the reliability advances have come from “understanding the typical types of not-surprising tool downtime and building expertise to quickly diagnose issues and implement solutions necessary across the fleet,” she said.
Much of the focus on EUV throughput has been on the power of the light source. It’s a critical and complex component that generates light by hitting a drop of molten tin with a laser. However, in practice Turkot suggested another EUV component–the light collector–is becoming a more important element in system throughput and uptime.
Intel has EUV systems running with power sources that range from 205W to 285W. At the level of the wafer “they are all giving the same power because of the collector…[but] wafer power changes day by day as the collector degrades,” she said.
Again, the good news is “there’s a clear line of sight to [ASML’s] target of driving exposure source power and downtime [by] doing collector replacement…There’s a fixed overhead removing and replacing the collector and bringing the system back up and reducing the contamination rate—ASML is making great progress,” she added.
Separately, ASML is now delivering protective films called pellicles. They keep wafers safe from fine particles that would otherwise contaminate them and lower yields.
Looking ahead, researchers are concerned random errors called stochastics that break or fail to complete a line drawn with an EUV system will limit their use at 5nm and beyond. Turkot expressed optimism that needed improvements will come in both effects with EUV light and with resist chemistry.
“Photon shot noise can be overcome by larger [light] exposures. The chemical aspects in resists will require a significant amount of work by the resist community.
“They have to understand the chemical responses from materials in secondary electrons and ions created by a high-energy exposure…There’s no consensus yet on a metric for material stochastics,” she said, despite many papers written on the topic.
“At [EUV] introduction I don’t expect [stochastics] to have an impact on yield, but when you look at EUV extensions [to 5nm and beyond] it’s a potential limiter. By the time we get there I expect there will be enough understanding from resist suppliers that it can be bypassed. The key is working on it now,” she said.
Turkot recalled how on first seeing today’s EUV systems “the sheer size and complexity of it was overwhelming,” and next-generation systems for 3nm and beyond are much larger.
Overall, she said described as “very rewarding” getting the chance to work on the mammoth systems needed to drive semiconductor technology forward.
“A lot of effort is going into debugging EUV, like any new platform. The whole intent has been that when it’s time for production we can’t tell the difference—it’s a seamless transition.”