EdgeCortix Partners with Cadence to Accelerate AI Chip Design

Article By : Cadence Design Systems Inc.

EdgeCortix has deployed multiple Cadence verification and digital tools to accelerate the design and verification of its edge AI chips.

EdgeCortix Inc. has deployed multiple verification and digital tools from Cadence Design Systems Inc.  to accelerate the design and verification of its edge artificial intelligence (AI) chips. In particular, the Cadence Verification IP (VIP) for the Arm AMBA 3/4 AXI standard and faster simulation performance with Cadence Xcelium Logic Simulation, enabled EdgeCortix to shorten its verification environment’s development to less than a month, while the Cadence Genus Synthesis Solution and Joules RTL Power Solution delivered a 2X reduction in power analysis time with better power, performance, and area (PPA).

The Cadence solutions were easy to deploy and use, so the EdgeCortix team was able to boost productivity. For example, the VIP for AMBA AXI comes with comprehensive, built-in protocol checks and debugging aids, which made it simple for EdgeCortix to catch protocol bugs early, reducing testbench debug time. Also, the Joules RTL Power Solution let EdgeCortix complete RTL power analysis quickly on multiple versions of their RTL IP, surpassing the planned timetables that were originally allocated for selecting the final RTL IP configuration used for GDSII conversion.

In addition to using the Cadence VIP for AMBA 3/4 AXI and Joules RTL Power Solution, EdgeCortix uses additional Cadence solutions, including the Xcelium Logic Simulator and the Genus Synthesis Solution. EdgeCortix was able to improve overall verification throughput and meet its verification schedule using the Xcelium simulator. Utilizing the Xcelium simulator’s multithreading capability, EdgeCortix was able to run simulations 1.8X faster, with large deep neural network models like YoloV3 running on its IP. Additionally, the Xcelium simulator’s superior debug capability allowed EdgeCortix to quickly debug assertions and transactions. The Genus Synthesis Solution’s multithreading capabilities allowed EdgeCortix to try more synthesis options to obtain the best gate-level netlist in less time.

“At EdgeCortix, we provide software and hardware acceleration IP based on our runtime reconfigurable architecture called Dynamic Neural Accelerator (DNA) architecture,” said Sakyasingha Dasgupta, CEO, EdgeCortix. “To develop our AI chips, we need solutions that can handle the design complexities while also ensuring our aggressive time-to-market schedules are met. The Cadence digital and verification solutions provided us with tools that made the verification process much more efficient, and the Cadence team offered standout customer support that allowed us to quickly ramp up our design project. To leverage cloud scalability and agility, we now plan to adopt Cadence CloudBurst platform, which provides a ready-to-use cloud-based design environment so that we don’t have to worry about IT setup and infrastructure management and can focus on delivering our products efficiently.”

Cadence Verification IP and Xcelium Logic Simulation are part of the broader Cadence Verification Suite, and the Cadence Genus Synthesis Solution and Joules RTL Power Solution are part of the digital full flow. The verification suite, the digital full flow and Cadence CloudBurst platform support the company’s Intelligent System Design strategy, enabling SoC design excellence.

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