Verifying additive phase noise and jitter attenuation of PLLs in high-speed digital designs

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Verifying additive phase noise and jitter attenuation of PLLs in high-speed digital designs

Increasing data rates in high-speed digital designs and wireless communications require SerDes PLLs and clock synthesizers with low additive phase noise and high jitter attenuation. Modern designs often follow a two-stage architecture, consisting of a jitter-attenuator and a frequency-synthesizer stage. Due to their high phase noise sensitivity, phase noise analyzers are the instruments of choice for these tests. To stimulate the PLL, an additional signal source with ultra low phase noise is required.

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