In this application note, we show how to combine jitter and power integrity analysis into a formidable tool for debugging SERDES, circuits, networks, and systems
• Describes the connection between signal integrity, specifically jitter, and power integrity
• Gives a brief review of jitter measurements and terminology, including eye diagrams and jitter decomposition
• Covers random and periodic jitter on clocks and relates periodic jitter to power integrity
• Describes sources of noise on power integrity, especially noise likely to cause jitter on serial data lines
• Gives an example of the impact of ripple on a power rail causing jitter on a clock
The application note uses the 6 Series B MSO to demonstrate jitter and power rail measurements. Its low noise contribution makes it well-suited for these measurements. The oscilloscope was equipped with both the Digital Power Management (DPM) option and Advanced Jitter Analysis (DJA). Although the 6 Series B MSO is used as an example, the 5 Series MSO offers the same measurements.This note focuses on the connections between power integrity and signal integrity.