One of the biggest semiconductor engineering challenges today is delivering
best-in-class devices while dealing with the technology scaling and cost limitations of monolithic IC design processes. To overcome these challenges, a growing number of companies are turning to heterogeneous integration and the 3D stacking of ICs and specialized chiplets (implemented in different processes geometries) into 3D ICs.
Chiplets are small ICs specifically designed and optimized for operation within a package in conjunction with other chiplets and full-sized ICs. In heterogenous designs, chips and chiplets are stacked and interconnected with vertical wiring using through silicon vias. They can even be combined with 3D memory stacks, such as high bandwidth memory, on a silicon interposer within the package of a device.
Heterogeneous IC integration enables companies to reach higher levels of optimal integration, performance, and lower power consumption than is possible in monolithic SoC ICs and multichip PCB system configurations. The use of 3D ICs is growing for a wide range of applications, such as high-performance computing, artificial intelligence and machine learning accelerators, mobile handsets, and automotive for edge cloud computing.