In this white paper,we discuss how traditional verification methods lack context-awareness or the ability to combine physical and electrical information for accurate analysis of potential ESD conditions in designs while leveraging foundry provided rule decks or your own custom rules.
1. Reliability verification based on both logical information (e.g. devices, nets, connectivity, and voltages, etc.) and physical information (e.g. polygons, widths and spacing, interconnect resistances and currents, etc.)
2. Rule deck based checks, which are consistent and repeatable, removing the need for human intervention and manual markers
3. Verification for a range of IC design sizes from intellectual property (IP) level to full chip level