Design teams are always looking for new ways to perform time-consuming DFT tasks more efficiently as the size and complexity of designs increase. ON Semiconductor reduced their DFT implementation time by 6X using Tessent hierarchical DFT methodology for memory BIST insertion. Read this whitepaper to learn how ON Semiconductor achieved success on their 10 million-gate design with Tessent.
What You Will Learn:
• How hierarchical DFT can be integrated into any design flow
• Why inserting DFT hierarchically cuts the total DFT time and effort
• What ON Semiconductor did to cut 6X DFT time on a 10 million-gate design
Read more about ON Semiconductor’s success with Tessent hierarchical DFT.