The analog design community desperately needs a transformative technology that finally solves analog layout automation.
In 1985, Intel debuted the 80386 microprocessor, it contained an amazing, for the time, 275,000 transistors on the die. In 2020 Apple released its first homegrown microprocessor, the M1, which includes 16 billion transistors. In just 35 years, Apple’s latest device contained over 58,000 x more transistors than its ancestors. The M1 is not even the largest processor available; Nvidia’s GA100 Ampere is said to contain around 54 billion transistors.
It is probable that the layout of 80386 was primarily designed by hand using the CAD tools of the day, but it is inconceivable that humans were involved in the layout of even a tiny fraction of the transistors in Apple’s M1. Digital layout was almost completely automated in the mid-1980s, around the same time that the 80386 was released. by EDA pioneers at Tangent Systems. Most of today’s digital engineers barely ever think about the layout of their circuits and certainly don’t consider the layout of individual transistors.
Today, digital blocks with 100s of millions of devices are routinely placed and routed in a few hours by advanced EDA tools with almost no human input. The impact on digital design productivity has been truly enormous. The team behind the M1 was much larger than the original 80386 team, but the overall layout productivity is at least three orders of magnitude, i.e., 1000x, greater than it was in 1985.
In contrast, analog layout has been a manual task for as long as integrated circuits have existed, and for most designers, analog IC layout is still very much a manual job today. Many analog layout designers are still placing individual transistors by hand, routing every wire by hand, and manually drawing every well shape and guard ring. While things have improved slightly in the past few years, with the arrival of templated layout, analog design remains a very time-consuming task.
Over the years, a number of incremental changes to the analog design flow have increased layout productivity in this domain also, but nowhere near as much. These changes include parameterized cells, schematic-driven layout, and, more recently, templated layout. The total effect of these changes is perhaps as much as a 10x improvement. A layout that in 1985 might have taken a designer three weeks to complete can now be accomplished in 2-3 days.
10x productivity improvement is good, right? So, what’s the problem? The problem is that at the same time, process changes have made analog design closure much harder. Today, layout dependant effects have become so vital that it is impossible to determine the optimum layout in advance. Engineers and designers often need to tweak and respin their design 4 or 5 times before meeting the specification. The effective increase in productivity is, in reality, 2-3x at most.
Analog layout has become “layout in a loop.” Circuit engineers need multiple layout iterations as quickly as possible for extraction and simulation to be able to close their designs. With each iteration taking hours or days, this is an expensive and time-consuming proposition.
The analog design community desperately needs a transformative technology that finally solves analog layout automation, just like Tangent and Tancell did for digital design in the 1980s. Analog design ought to benefit from the same increase in computing power that so dramatically helps digital design. We need to move away from incrementally improving the existing manual layout techniques and truly deliver analog automation. Otherwise, analog designers will continue to be the IC design world’s Cinderellas, forever repeating the mostly thankless manual layout tasks.
So, why has analog layout been so hard to automate? The primary issue is the multifactorial nature of analog design, and even a simple opamp may need optimization for input bias current, offset voltage, CMRR, PSRR, gain margin, phase margin, noise, distortion, voltage swing, and more. The layout of an analog block affects all of these factors.
In the digital case, the standard cell approach effectively abstracts the layout problem to the point where there are just three main factors to optimize, timing, power, and area. Creating the standard cell library is a complex custom task, but once you have a two-input nand with a variety of output driver strengths, you don’t need to create a new transistor level layout over and over again.
This abstraction also means that digital automation tools don’t have to consider the vast majority of complex DRC rules. They must consider the routing layer rules but not the hundreds of complex rules that now govern the layout of the active layers. The task of automating digital layout is largely an exercise in applied graph theory and computer science. This is oversimplifying a bit, but not much when compared to the task of automating analog layout.
Digital MOSFETs are driven hard into their saturation region and act as switches, either on or off. In analog design, the MOSFETs are working in their linear (ohmic) region and are very sensitive to the layout environment around them. It simply isn’t possible to treat analog devices as abstract blocks that can be placed and routed in the same way as digital cells. The routing also affects analog design in complex ways. In a digital environment, a longer route has the simple and predictable effect of delaying the signal. In an analog circuit, longer routing adds capacitance to the circuit which can negatively affect many factors, noise, distortion, frequency response, etc.
Over the years, many attempts have been made to automate analog layout. These have mostly involved trying to adapt digital standard cell approaches. None of these approaches have been successful; these algorithms have no understanding of the effect the solutions they produce will have on the performance of the circuit. Some attempts have used floorplanning techniques from the digital domain. Floorplanning algorithms are designed to efficiently pack uneven shapes together into the smallest space. But, analog layout is not primarily a packing problem; in fact, while compact and area-efficient packing is important, it comes a long way down the priority list for analog layout.
A further issue is the routing. In the digital world, placement and routing are sequential operations. The standard cells are first placed by a placement algorithm. The placer is “routing aware” and considers routing congestion and the effect of parasitic resistance and capacitance resulting from the wires, but it does not actually place the wires and standard cells simultaneously. This separation of routing and placement does not work with analog layout. Poly heads are a simple example of why that is the case. Connections to the gate of a MOSFET require space on the polysilicon layer for a short extension of the gate and a via connecting to a higher metal layer. This geometry pushes devices further away from each other in the vertical direction, directly affecting the placement of devices. Additionally, these poly heads increase the amount of polysilicon geometry and affect the poly density. Above a certain threshold, it might be necessary to space the devices horizontally to avoid breaking one of the design rules.
All the previous approaches have all suffered from the same problems. They weren’t ever truly analog aware; the approach was too algorithmic, trying to replicate the solution achieved by humans with brute force or random chance. To get a “good” layout required an engineer to highly constrain the problem, which is a non-trivial task often requiring many iterations to find a good set of constraints for each design. Additionally, the core of these algorithms didn’t understand the design rules, CAD teams needed to maintain enormously complex technology files, full of rules; and then the solutions produced often still contained large numbers of design rule violations that needed fixing. Overall the effect on productivity provided by previous approaches has been marginal at best and often detrimental.
After so many years of failed attempts, designers are understandably skeptical about whether analog layout can ever be automated. Many believe that it is simply too complex a problem, and that will never be solved.
Analog layout automation tool attributes
So, what attributes does an analog layout automation tool need to achieve this seemingly impossible task?
After many years of research and development, the team Pulsic has recently announced a new tool, called Animate Preview, that tries to encompass all of these attributes. Animate Preview integrates into the circuit engineer’s schematic environment. The tool automatically creates a layout view for the circuit when the engineer is still editing their schematic, giving them fast feedback on design decisions. The engineer can access detailed layout visualizations of their circuit and accurate area estimations.
Pulsic calls these layouts ‘previews’; they are high quality, automatically generated layout views of the circuit. Pulsic is not claiming these layouts are final quality, but they are very near and much closer than any previous tool has been able to produce. The previously discussed problem of generating constraints for the circuit is removed. Animate understands analog circuit topologies and automatically generates appropriate constraints for the circuit, although the engineer can edit the constraints if they want to achieve a particular result. Animate Preview’s algorithm has a deep understanding of the design rules, and the results that it produces are DRC correct, giving the engineer confidence in the previews. Similarly, the placement is produced with routing in mind; in fact, many critical structures will be routed in the layout preview.
The idea behind Animate Preview is to eliminate many of the loops between circuit engineers and layout designers, helping them to close their designs more quickly and be more productive.
Mark Williams, CEO of Pulsic, says, “After several years of dedicated effort we are proud to announce the release of Animate Preview; a transformative technology, that delivers true analog automation for the first time. Animate Preview is already reducing design iterations, speeds up the layout process, and is closing the productivity gap for analog design teams around the world.”
Pulsic has taken the unprecedented step of making Animate Preview available as a freemium download. Engineers can download and install Animate Preview without charge from their website https://animate.pulsic.com. The free version is fully featured and allows users to produce and view layout previews for their circuit and produce a design area report. An upgrade to Animate Preview Plus is available, which allows the previews to be saved as layout in OpenAccess.
Mark Waller is Director of User Enablement at Pulsic. He started his career in EDA 25 years ago as a software engineer at Zuken Redac. In early 2000, Mark was one of the original founders of Pulsic and was its VP of R&D for over 15 years. Following a career break as a high school physics teacher, Mark is now back at Pulsic and now leads user enablement for Pulsic’s Animate product line.