Denso Leads Quadric’s $21-Million Series B

Article By : Sally Ward-Foxton

The Japanese Tier 1 will license Quadric’s novel AI and computer vision accelerator IP.

Quadric, the startup building accelerator chips for computer vision and AI acceleration, has raised $21 million in a Series B funding round. The round was once again led by NSITEXE, a group company of Japanese automotive Tier 1 supplier Denso, with additional investment form MegaChips alongside existing investors. The company has raised a total of $39 million to date.

Quadric M.2 Dev kit
Quadric’s first chip is available on an M.2 module (Source: Quadric)

Quadric’s chip architecture, a novel hybrid data-flow and Von Neumann design, is designed to accelerate both AI and standard computer vision workloads including DSP and basic linear algebra subprograms (BLAS). The aim is to replace the combination of NPUs and powerful CPUs in edge devices with a single chip which can accelerate the entire application pipeline.

The company’s first chip, the q16, is an array of 256 (16 x 16) Vortex cores, offering 4 INT8 DNN TOPS. Running ResNet-50 at 200 inferences per second (for INT8 parameters at 224 x 224 image size), it consumes an average of 2W.

“Having evaluated Quadric’s q16 processor, its ability to run many types of algorithms efficiently and flexibly allows Quadric’s platform to enable AI in new services and products,” said Tony Cannestra, director of corporate ventures at Denso, in a statement. “We look forward to continuing to work closely with Quadric and plan to integrate their IP into Denso’s SoC products.”

Denso is planning to use Quadric’s IP together with its own processor IP to develop safety solutions for ADAS, autonomous vehicles and smart sensors.

The decision to offer IP as well as silicon was based on customer pull.

Quadric CEO Veerbhan Kheterpal
Veerbhan Kheterpal (Source: Quadric)

“The edge space is extremely fragmented… there is a lot of hunger out there for high performance computing technologies like the one we have, especially with our software capabilities,” Quadric co-founder and CEO Veerbhan Kheterpal told EE Times. “There’s so many different interfaces that are needed around the actual use case, we can’t really build all those chips for the edge. The requests that we get for IP are very organic; as we talk to customers, we are getting more and more pull in that direction.”

Quadric is working with early-access customers on its IP offering today, but plans broader IP availability further down the road.

Kheterpal said the Series B funding raised will be used to focus on go-to-market strategy, including “going after the right verticals, bringing a more mature product to market and starting a broad range of evaluations.” Quadric has been working on software enhancements for its q16 product. The company has added preprocessing and post processing capabilities, including non-max suppression (a technique used in object detection). Customer engagements include ADAS, edge video analytics, edge authentication and robotics.

The company has some design wins in the automotive ADAS space and is now pursuing edge computing and embedded edge computing.

The funding will also be used to develop Quadric’s second-generation architecture, which Kheterpal said will offer improved performance per Watt. The previously planned first-gen q32 chip (with 1024 cores) will now be built on the forthcoming second-gen architecture, due to tape out around October 2022. The option to include an Arm or RISC-V core to add a system host processor to the q32 “is still on the table,” depending on market pull.

An M.2-format developer kit, with a q16 processor alongside 4 GB of external memory, is available now. Samples of Quadric’s second-generation silicon products will be available at the end of this year.

This article was originally published on EE Times.

Sally Ward-Foxton covers AI technology and related issues for EETimes.com and all aspects of the European industry for EE Times Europe magazine. Sally has spent more than 15 years writing about the electronics industry from London, UK. She has written for Electronic Design, ECN, Electronic Specifier: Design, Components in Electronics, and many more. She holds a Masters’ degree in Electrical and Electronic Engineering from the University of Cambridge.

 

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