As semiconductors become the choke point in global tech wars, the U.S. looks to advance security to the IC design stage...
The latest in a series of Pentagon semiconductor initiatives seeks to embed security features into chip designs that would allow silicon architects to probe economics-versus-security tradeoffs while baking in security throughout device lifecycles.
The chip design effort represents continuing U.S. efforts to secure its electronics supply chain as semiconductors emerge as a choke point in what is shaping up as a technological Cold War with China.
DARPA announced two teams last month to ramp up its year-old Automatic Implementation of Secure Silicon (AISS) program led by Synopsys and Northrop Grumman. Both teams will develop Arm-based architectures that incorporate a “security engine” used to defend against attacks and reverse-engineering of chips. An upgradeable platform would provide the infrastructure that military planners say is needed to manage hardened chips throughout their lifecycles.
Launched in April 2019, AISS is designed to balance security and economic considerations in securing the IC design process and chip supply chains.
Besides Arm, the Synopsys team includes aerospace giant Boeing, the University of Florida’s Institute for Cybersecurity, Texas A&M University, University of California at San Diego, and U.K.-based embedded analytics vendor UltraSoC.
Northrop Grumman heads a team that includes IBM, University of Arkansas and University of Florida.
The two-tiered effort includes competing “security engine” approaches that address key chip vulnerabilities such as side channel attacks, hardware Trojans, reverse engineering and supply chain exploits. Side channel attacks include tracking device power consumption as a means of stealing an encryption key.
In a later phase, the Synopsys team will seek to leverage EDA tools to integrate its security engine into SoC platforms. The approach would combine “security-aware” EDA tools developed under the DARPA program using commercial IP from Arm, Synopsys and UltraSoC.
Chip designers would then specify key constraints for power, area, speed and security for AISS tools. Those tools would then “automatically generate optimal implementations based on the application objectives,” program officials said.
“The ultimate goal of the AISS program is to accelerate the timeline from architecture to security-hardened [register transfer level] from one year, to one week — and to do so at a substantially reduced cost,” said Serge Leef, the DARPA’s program manager for AISS.
Ultimately, the agency hopes to automate the process of incorporating “scalable defense mechanisms into chip designs” as it seeks to protect its semiconductor supply chain.
Related DoD technology efforts include industrial base initiatives aimed at securing U.S. chip supply chains using digital twin capabilities that can validate integrity in either individual devices or a batch of chips. A Defense Department/Air Force effort announced earlier this year also would add a layer of secure “provenance tracking” as well as the “heterogeneous integration” of chip types on a single die.