Chiplets to Open Up Completely New More than Moore Roadmap

Article By : Don Scansen

The basic idea behind chiplets might not be entirely new, but the concept goes several steps further than the idea has been taken before.

Our chiplet discussion left off with the historical perspective that “this isn’t new.” Heterogenous integration, system-in-package (SiP) and the the related package level integrations have all been done before. Keen observers of technology are right to point out that everything old can be new again. Even though the multi-chip modules and hyrid circuits harkened back to the same point in history, we shouldn’t compare chiplets to bell bottom jeans.

To help differentiate chiplets from the conventional terminology in my last column, I “attended” a virtual Open Compute Project (OCP) workshop on chiplets last week. As it was defined on a few occasions in this workshop, chiplets will expand the multi-chip module concepts in a unique way to open up a completely new more than Moore roadmap.

OCP? Who now?

The Open Compute Project (OCP) was relatively unknown to me before the workshop. In 2009, Facebook initiated “a project to design the world’s most energy efficient data center, one that could handle unprecedented scale at the lowest possible cost.” That’s according to the organization’s web site.

As the project showed promise, Facebook released its findings to the public, and the OCP was launched by Facebook, Intel, Rackspace, Goldman Sachs, along with Sun Microsystems co-founder Andy Bechtolsheim.

Current board members include representatives of Facebook, Rackspace, Microsoft, Google, and Intel, all companies with a keen interest in the transitioning to chiplets.

Chiplets belong to an OCP subgroup, Open Domain Specific Architecture (ODSA), which studies programmable devices as well. In their overview, “Domain-specific architecture: Programmable devices optimized for specific applications or class of applications. Meet the demands of high-intensity workloads in the data center and at the edge — e.g. machine learning, video processing.”

The ODSA introduction explains chiplets in this way: “Chiplets: Implement an integrated product as a collection of die in a single package, instead of a single die. Each die is a chiplet. Can reduce development and manufacturing costs.”

Oddly enough, this gets right back to the traditional versions of SiP that raise hackles. The definition needs to be tightened up for engineers with a better appreciation of history.

Developing the business

Without a business model, the debate on terminology is moot. Developing that model is a frequent discussion topic, and the title of this workshop addresses it: ODSA Chiplet Business Enablement Workshop. “Business enablement” got my attention. Videos and slides are expected to be available at the ODSA site, but you will have to check back later.

Both attractive economics and lingering questions surround the transition to a vibrant chiplet market.

The current single die business model is linear and well understood. Moving to a chiplet model leaves several unanswered questions (source: OCP)

There are a few but very strong considerations driving the transistion to a chiplet design disaggregation ecosystem: many key system IP blocks do not scale as fast as the logic; large die yield is poor; wafer production times are longer for advanced technology nodes; chiplet improves time-to-market for new products.

CEO of Alphawave IP Inc., Tony Pialis, believes the tipping point for chiplet adoption is the economics of 3nm wafer processing technology. Considering the limited access to the cutting edge, Pialis heard no objections to his assertion.

Who pays the tax?

Of course, it’s not all milk and honey when it comes to chiplets. This is a real world engineering problem, and a few growing pains will be endured.

Several “chiplet tax” items were identified in the workshop.

  • Increased design complexity
  • Intra-chip data interchange moved off chip:
    • Useful area lost to additional peripheral area for increase in I/O for die-to-die communication
    • Power and latency increase per design
  • Redundancy to address known good die issues
  • Increased cost of packaging
  • Increased upfront NRE per design.

Chiplet taxes introduce two new concepts and acronyms central to the discussion.

Four legs of support for the concept (source: OCP)

The known good die (KGD) concept is, well, known beyond this sphere but it’s getting more airtime these days. The number of die going into each product and the diversity of complexity (that’s heterogeneous if you’re keeping score at home) pits testing simple and cheap die against complex and expensive die integrated together. A working final product depends on the weakest link.

The second new (to our discussion) term is die-to-die (D2D) for short range data communication inside a package. “D2D” gets thrown around so much I think I’m hearing myself at one of my daughters’ hockey games. On the ice, passing the puck “D2D” is the key to success in the offensive zone. It’s even more critical when it comes to chiplets.

The D2D communication belongs with one of the three chiplet topics that have become ubiquitous: Standards, Interfaces, and Known good die (KGD)

I collected a few anecdotes from the workshop related to these main themes.


  • Electrostatic discharge (ESD) will need to be addressed. Of course, this will depend on various other trends related to how chiplet products will be supplied to assembly sites.
  • Wafer or tape and reel delivery to packaging and assembly vendor? Chip shooters could be used with tape and reel.
  • Allan Cantle, CEO of Nallasway Inc., mused that ODSA might focus on more specific standardization for the smaller players since the big guys will probably go their own directions.


  • Need to settle on one parallel and one serial
  • Tony Pialis promoted PCIe. It can also serve as a predictor of how things may roll out in general. PCIe started with very large manufacturers, but now it is ubiquitous. Look to that playbook for D2D.
  • Lessons learned from high bandwidth memory can be re-used both for interfaces and standards.


Intel – “UUD” was coined. Perhaps to put a finer point on KGD, one workshop participant suggested unknown ungood die. What if you have a big expensive FPGA and a bunch of small, very cheap die in your product, and it is rejected because one of the small die fails? – The economics of who owns the failure is the issue that needs to be resolved.

Chiplet design is where SoC meets EMS (source: OCP)

Crystal balling

Andreas Olofsson, founder of Zero ASIC, hoped to tease out some predictions: “How many chiplets will be incorporated into a single design by 2025?”

Swami Prasad from JCET responded that a 100 Χ 100mm package is possible today.

Eelco Bergman of ASE Group said that current designs contain 15 to 20 today, but these include a main die and multiples of only 1 or 2 other different designs (small scale heterogeneity). Integrating 20 different chiplets would be “tough” (would have to come in tape and reel).

The other enticing quesiton was, “Will EDA providers or IP vendors supply chiplets?” I believe it was Tony Pialis who thought that vendors need to “stick to their lanes” and not get into competition with customers, but we will see.

Are chiplets new?

Ramin Farjadrad, CTO & VP of Networking/Automotive PHYs at Marvell, took us back to the origins of this debate as he described chiplets by an older standard. Farjadrad described the approach as shrinking designs by using off the shelf chips and making a SiP to reduce the footprint.

I need to turn this around before the hate mail flood.

A subtlety escaped me during early exploration of the chiplet field. The chiplet concept and heterogeneous integration goes a step beyond by collecting existing chip designs onto a common package substrate or interposer.

A chip becomes a chiplet once it is stripped of the robust I/O capability needed to drive signals over long distances and the into the larger impedances at the package and board level.

That’s the essence. A chiplet trades powerful area hungry I/O that for a larger number of smaller, short range D2D I/O that would conventionally be handled by the intrachip signaling on a monolithic design.

Chiplets are stripped down chips. Duh.

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