Chiplets Promise to Revive Moore’s Law

Article By : Gary Hilson

Die-stitching techniques, the basic concept behind chiplets, aren’t new or necessarily propriety, but the approach could benefit from templates.

Chiplets are a great example of a solution that’s been around for a while but is quickly finding more problems to solve.

With Moore’s Law now 55 years old and pace of semiconductor manufacturing advancement decelerating, chiplets offer an approach to semiconductor design and integration that hold the promise of speeding up things up again. Recent research released by Omdia forecasts the global market for processor microchips that use chiplets in their manufacturing process to hit $5.8 billion in 2024, a significant jump from $645 million in 2018.

Tom Hackenberg, Omdia’s principal analyst for embedded processors, said chiplets will enable the semiconductor business to return to the customary rate of progress initial set my Moore’s Law by effectively bypassing it. Chiplets replace a single silicon die with multiple smaller dies that work together in a unified packaged solution, which provides much more silicon to add transistors compared to a monolithic microchip. He said this would enable a return to the two-year doubling cycle that has been the economic foundation of the semiconductor business since 1965.

As revolutionary as their promise appears, chiplets are not a new concept, said Hackenberg. “The whole process of shrinking solutions has been around for a long time.” Over time, progress has been made at the system to the board level and then down to the chip level. “Now we’re talking about a next generation iteration where functionality is being designed in at a sub-chip level where, or what we would call a chiplet.”


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Major semiconductor manufacturers are turning to chiplets now to counter the impact of the physical limitations of Moore’s law, he said. “The economic barrier of Moore’s law is hitting us much sooner.” And just as the increasing costs of miniaturization has led them to explore 3D, new materials, and other paths to produce increased performance without sacrificing yield, chiplets represent another such technology exploration.

Omdia predicts the global market for processor microchips that use chiplets in their manufacturing process will expand to $5.8 billion in 2024

It’s not just the need to shrink more while getting good yield that makes chiplets appealing, said Hackenberg, but with electronics turning up everywhere in droves, there’s a move to higher density, more heterogeneous solutions where little pieces of that semiconductor are performing very specific application functions. “One small subsystem might be a signal processor, another small subsystem might be a graphics processor, and another might be a security engine or an AI accelerator,” he said. “This new and growing heterogeneous chip market lends itself to the technology that is provided by chiplet manufacturing.”

Another appeal of chiplets is you can build them using components and techniques that are tried and true, thereby minimizing the likelihood of a failure, said Jim Handy, principal analyst with Objective Analysis. It used to be that if you built a package with a $100 processor and several low-cost SRAMs, all it took was one SRAM to fail and everything would have to be thrown out, including the processor. He said the advances in die testing and packaging reduce the risk. “You’re going to be able to pick things, know they’re going to work, and know that you’re not going to have to throw away that $100 processor.”

Xillinx is one company that’s leveraged chiplets since before they were cool. “We’ve done them in different ways and in different forms for many years,” said Manuel Uhm, the company’s director of silicon marketing. Xilinx has a number of products leveraging chiplets that have gone to market—its stacked silicon interconnect (SSI) technology is its fourth generation, for example, and its Virtex UltraScale+ uses chiplets to integrate the company’s large FPGA die with High Bandwidth Memory (HBM).

Xilinx 3D IC devices, like the VU19P, utilize Stacked Silicon Interconnect (SSI) technology, enabling high-bandwidth connectivity between multiple die and provide massive inter-die bandwidth-per-watt compared to alternative multi-chip approaches.

But there are other things that never made it to market, said Uhm. “We innovate, we experiment, and we see what works best for what our customers need. In some respects, it’s easier from a system level to get everything working on a monolithic die. There’s pros and cons to both.” The pro is that chiplets enable Xilinx to deliver an incredible amount of compute density by stitching together smaller die to create larger devices.

Chiplets also enable companies to stitch together dies from other vendors so they can focus on their strengths when building a device, said Uhm. It also enables them to get the optimum performance for the best price because they’re not going to get a huge performance boost by going to the next process node. Some chiplets might include one part of a die that’s done at 60 nanometers, he said, and another at 28 nanometers to meet the cost targets that the application requires to be successful. This modularity allows for flexibility as well as reliability because you can stick with technologies that have a proven track record and reduce risk.

Because chiplets have been around for a while with different companies such as Xilinx developing their own methods of stitching them together, it raises the question: Is there a need for standards?

The zGlue Integration Platform (ZiP) delivers prototypes based on pre-validated chiplets within three weeks

The Open Compute Project (OCP) is looking to answer this question, not so much by setting hard and fast rules, but by trying to pull together best practices for the commonly used processes that go into putting chiplets together, said CTO Bill Carter. “There’s a lot of things that we need to flush out.”

The OCP Open Domain-Specific Architecture (ODSA) subproject is dedicated defining and developing a chiplet-based architecture with the introduction of new interfaces, link layers, a marketplace and exchange, and an early proof-of-concept. While a standard could emerge, the immediate need is to compile information around the various types of chiplets so they can be successfully assembled into a single package, including bump patterns, dimensions, package tolerances and die tolerances.

Another important aspect of chiplets is test coverage, Carter said. To effectively test certain functions at the die level or at the package there needs information about the processes that went into each chiplet needs to be shared. There also needs to be a process to debug a problem with a chiplet if something is uncovered, especially since multiple suppliers could be involved, so the problem can be isolated, he said. “You could have two different companies providing the die and the third company doing the manufacturing. There’s some business processes that have to be ironed out.”

ODSA participant zGlue is one company that’s looking to bring clarity to the chiplet ecosystem. It offers a platform and process for building custom chips on demand to help hardware vendors respond to increasingly intense time-to-market pressures. Co-founder and CTO Jawad Nasrullah said there’s need for templates that act as guides for bringing chiplets together and creating a repository of tracks their various characteristics for designers, such as power and testing abilities.

A good analogy for chiplets is object-oriented programming, a paradigm based on the concept of objects that can contain data in the form of fields and code in the form of procedures—a similar paradigm shift is happening in hardware. But for chiplets, said Nasrullah, there’s a pressing need for interfaces, not just electrical ones but the ones that simplify design, manufacturing and collaboration—zGlue’s recently launched its Open Chiplet Initiative (OCI) to be that marketplace. If everything stays in-house, it’s really just multi-chip module design, he said. “You want to work across companies.”

The OCI provides a gallery of open-source designs, tools, and file formats that span the chiplet ecosystem from toolsets all the way to completed designs. Tools in the OCI include that zGlue Exchange Format (ZEF), a bring-up/testing software library (PyChipBuilder), design examples, development kits, and a central location for showcasing and distribution of open source projects.

As more companies look to leverage chiplets, processes and approaches that were traditionally in-house but necessarily proprietary will be come more exposed, said Carter. “This information doesn’t need to be proprietary. It was only treated as proprietary because it was never exposed outside the company.”

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