Samsung Electronics Expands Portfolio of ‘Green’ Chips
Five memory products achieved carbon reduction certification, while automotive LED packages received carbon footprint verification.
Amkor Plans New Vietnam Factory to Expand Advanced Packaging Technology Capacity
Amkor plans to build a state-of-the-art smart factory in Bac Ninh, Vietnam to expand its advanced packaging technology capacity.
YMTC Licenses Xperi’s Hybrid Bonding Technology
Xperi has licensed its Direct Bond Interconnect (DBI) hybrid bonding portfolio to YMTC for its 3D NAND memory products.
Taiwan Electronics Update
Taiwan really contributes more value to the iPad Pro than accounted for.
What to Expect at the VLSI Technology Symposium
The papers from the upcoming VLSI Technology Symposium suggest there's some agreement on general direction, but little agreement on terminology.
GUC Unveils Die-on-Die Interface IP Using TSMC N5 and N6 Process
GUC has announced GLink-3D die-on-die interface IP using TSMC’s N5 and N6 processes, and 3DFabric packaging technology for AI, HPC,…
Optimizing Package System Integration Maximizes System Performance
Closer collaborations between package and system designers to optimize package system integration will help maximize system performance.
5 Key Considerations for Next-Gen IC Packaging Design
Next-generation IC packaging is the best path to achieve silicon scaling, functional density, and heterogeneous integration while reducing the overall…
Will FOWLP Keep Moore’s Law Valid?
Moore's Law in process technology is on its last legs, so advanced packaging is taking up the baton.
A Short History of Chiplets
The idea of the disagreggation of ICs into smaller physical pieces of silicon—chiplets—has been generating buzz for some time.
Squaring the Circle: A Look at Deca Technologies’ Innovations
Deca knows new approaches are needed to continue to scale production, as well as to address the demands of "More…
ISSCC: Roadmap on 3D Interconnect Density
The common theme coming out of the chiplet forum at ISSCC was the need for a 3D interconnect density roadmap.
