Apple's lawsuit claims that Rivos has committed trade secret theft of its homegrown chip designs.
Applied Materials has launched innovations that help customers continue 2D scaling with EUV and next-generation 3D GAA transistors.
Lam Research's selective etch tools aim to help chipmakers leap from planar to 3D structures.
Find out where Intel stands in its bid to compete with fab business behemoths TSMC and Samsung.
In a post-Moore's Law world, there will be lots of unknowns. Will the benefits of chiplets be realized? How will…
The recently announced UCIe 1.0 specification provides a complete standardized die–to–die interconnect with physical layer, protocol stack, software model, and…
ESD industry revenue increased by 14.4% year-on-year to $3.468 billion in Q4 2021, according to the ESD Alliance.
Revenue of the global top 10 IC design companies reached $127.4 billion in 2021, up by 48% YoY, according to…
Industry leaders have formed a consortium that will establish a die-to-die interconnect standard and foster an open chiplet ecosystem.
Cadence has received a TSMC OIP Ecosystem Forum Customers’ Choice award for a paper titled, "Integrated Platform for 3D-IC Design."
It's the dawn of the self–designing chip. AI-based chip design can relieve some of the strain on engineering teams and…
As part of the alliance, Siemens plans to collaborate closely with IFS to optimize best-in-class IC design tools, flows and…