2017-03-15 - Xilinx

reVISION stack boosts vision-guided machine learning

The stack offers up to 6x better images/second/watt in machine learning inference, according to Xilinx.

2017-02-06 - ZTE

ZTE achieves deep learning benchmark via Intel FPGA

ZTE achieves a record–beyond a thousand images per second in facial recognition–known as “theoretical high accuracy” for its custom topology.

2017-02-03 - Harting

Self-assembly connectors target custom cable assembly

The new 1.27mm pitch connectors are equipped with insulation displacement connection termination technology.

2016-12-26 - Synopsys

Synopsys obtains injunction in ATopTech suit

Synopsys has obtained a permanent injunction in its copyright suit against EDA start-up ATopTech.

2016-12-06 - Microsemi

Microsemi offers first open architecture RISC-V IP core

The RV32IM RISC-V core is available for Microsemi's IGLOO 2 FPGAs, SmartFusion 2 system-on-chip (SoC) FPGAs or RTG4 FPGAs.

2016-10-27 - Synopsys

Samsung certifies Synopsys platform for 10LPP process

The Galaxy Design platform certification for Samsung's 10LPP process includes design techniques for enabling less power consumption.

2016-07-29 - Graham Prophet

Multi-purpose DSP enables efficient C programming

Compared to the Tensilica Fusion F1 DSP, Fusion G3 DSP shares the same base Xtensa ISA, while adding richer and higher-throughput DSP instructions.

2016-07-22 - Ams AG

Hitkit supports designs in analogue 180nm CMOS tech

The PDK provides a plug-and-play tool set with improved analogue features and device performance as well as highly accurate simulation models.

2016-07-13 - None

Seoul, Hanoi to strengthen bilateral ties for IT, telco

Hanoi anticipates the cooperation with Seoul in assisting with the city’s process of construction and development in e-governance, IT and teleco sectors.

2016-07-08 - Tanmoy Sen, Chethan Devaraj

Building pin-level digital logic with Smart I/Os

Smart I/O offers flexibility for interconnection using the interconnection matrix. Users need not write any code to configure the Smart I/O block.

- Tanmoy Sen, Chethan Devaraj

Building pin-level digital logic with Smart I/Os

Smart I/O offers flexibility for interconnection using the interconnection matrix. Users need not write any code to configure the Smart I/O block.

2016-07-07 - Duane Benson

USB Type-C in Micro-B domain

USB 3.1 spec can be a bit intimidating when compared to the USB Micro-B connector and the FTDI USB 2.0 to UART chips most of us microcontroller folks have gotten used to. However, it is possible, not difficult, and officially supported, to wire in a Type-C connector to an existing USB 2.0 design.