Cascade field-effect transistors, an innovation out of Purdue University, could help address chip scaling, power consumption challenges.
Purdue University researchers report an advance that could lead to next-generation transistors that are smaller, denser and offer lower voltages and power consumption.
One outcome could be faster CPUs that compute more operations using less power. Known as CasFET (Cascade Field-Effect Transistor), the advance addresses chip scaling challenges and the soaring costs of manufacturing bleeding-edge chip designs.
The challenge involves meeting the performance requirements of nano-transistors that require a sufficiently high “on” and lower “off” currents, along with minute differences when switching between them.
Those are among the issues that have slowed the downscaling of transistors, something noticed with Intel’s recent transition from 10- to 7-nm process technology.
CasFET is promoted as mitigating those issues, making it easier for manufacturers to produce densely-packed, low-power transistors. The technology features superlattice structures perpendicular to the transistor’s transport direction, allowing them to behave similar to quantum cascade lasers instead of traditional FET devices.
Purdue engineers have so far committed about 150 hours developing a simulation engine used to advance CasFET technology.
“My team and I are developers of a massive nanotechnology and quantum transport simulation engine at Purdue that has found high acceptance among big tech companies,” said Tillmann Kubis, an assistant professor of electrical and computer engineering.
“We daily model all quantum transport aspects of transistors in subatomic resolution,” Kubis added. “That exposes us automatically to a lot of transistor technology and [the] latest challenges.”
Kubis also worked on modeling quantum cascade lasers as part of his doctoral studies. “Those lasers switch with external electric fields their transport nature from coherent/ballistic to stepwise and phonon-assisted tunneling. That switching effect is what we add to the ‘standard’ field-effect switching of FETs.
“That addition results in nano-transistors that are way more sensitive to gates than the state-of-the-art ones,” Kubis added. “This also applies to the gate all-around FETs. All those transistors rely on a single switching mechanism. Ours comes with two.”
Kubis said his team is currently designing prototype CasFET devices. “I am confident the new switching method will make an impact,” he added.
This article was originally published on EE Times.
Cabe Atwell is an electrical engineer living in the Chicago area.