Cadence has received a TSMC OIP Ecosystem Forum Customers’ Choice award for a paper titled, "Integrated Platform for 3D-IC Design."
Cadence Design Systems Inc. has received a TSMC Open Innovation Platform (OIP) Ecosystem Forum Customers’ Choice award for a paper titled, “Integrated Platform for 3D-IC Design,” which was presented during the TSMC 2021 North America OIP Ecosystem Forum.
Cadence’s Thunder Lay, software engineering director, presented the paper, highlighting the benefits of the recently introduced Cadence Integrity 3D-IC platform, the industry’s first comprehensive, unified platform for 3D-IC design planning, optimization, implementation and signoff.
With 3D-IC packaging increasing in popularity due to today’s design requirements, the Cadence paper received the highest average score among forum attendees. Designers learned how the Integrity 3D-IC platform enables system-driven power, performance and area (PPA) for individual chiplets through integrated thermal, power and static timing analysis capabilities. The platform is ideal for customers creating emerging hyperscale computing, consumer, 5G communications, mobile and automotive applications and supports TSMC’s 3DFabric technologies.
“The Integrity 3D-IC platform helps customers address top-level 3D-IC design aggregation and management, system-level analysis and signoff challenges, and the costly overdesign of individual dies,” said Don Chan, vice president, Research & Development. “What really sets the Integrity 3D-IC platform apart from other industry solutions is that it is tightly integrated with Cadence analysis tools, providing customers with an extra benefit of system-driven PPA. The Customers’ Choice Award recognition reflects our strong 3D-IC collaboration with TSMC, and we look forward to working with mutual customers to enable them to achieve design goals with our new platform and TSMC’s 3DFabric technologies.”
“Cadence’s paper explained how the integrated Integrity 3D-IC platform in conjunction with TSMC’s advanced 3DFabric technologies enable a system-level approach to product design to improve PPA and time to market,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “I’m delighted to congratulate Cadence on winning this Customers’ Choice Award and am looking forward to our continued collaboration with Cadence to enable cutting-edge 3D-IC designs and help customers accelerate innovation of their differentiated products.”
The Integrity 3D-IC platform offers an efficient solution to deploy 3D design and analysis flows for the creation of robust, silicon-stacked designs. The platform is part of the Cadence digital and signoff product portfolio and aligns with the broader Cadence Intelligent System Design strategy, enabling system-on-chip (SoC) design excellence.